2024 SKYTalk Speakers
CHIPS for America and Sustained U.S. Leadership: A Vision for Innovation Through the National Semiconductor Technology Center (NSTC)
Monday, June 24 | 1:00 pm - 1:45 pm
The semiconductor industry has always moved fast, but changes in the industry over recent years have been historic. We will discuss a variety of challenges in the ecosystem, and how the NSTC can unite the community to address those challenges. Some of these are technical – logic, mixed signal, memory, photonics, design / co-design, and architecture all need new breakthroughs to continue to advance the state of technology. Others are ecosystem challenges. Access to design tools, IP, and collaboration environments, as well as increasing use of AI in the design and verification flow will all transform the way that the industry does its work. Access to advanced R&D facilities and leading-edge shuttles can accelerate the pace of research. The traditional venture model has been mismatched with hardware investments for decades, and this has been a drag on innovation, but there are new ideas for how this can work better. In closing, we will provide updates on the priorities for this year and show how the NSTC can change the long-term trajectory for innovation.
ABOUT: Dr. Jay Lewis is the Director of the National Semiconductor Technology Center, or NSTC, Program, for the CHIPS R&D Office at the Department of Commerce. In this role he is working to establish the NSTC program, a public-private consortium that will serve as a cornerstone of semiconductor research for the country. He previously worked at Microsoft, at DARPA, and had an early career in semiconductor research.
Dr. Lewis is a Fellow of the American Vacuum Society and is an IEEE and SPIE Senior Member. He has published over 50 articles in technical journals and conference proceedings and holds eleven U.S. patents. He received a Bachelor’s degree in Materials Science from the Georgia Institute of Technology, and a Ph.D. in Materials Science and Engineering from the University of Florida.
New EDA Methodologies are Transforming Engineering Lifecycle Management
Tuesday, June 25 | 1:00 pm - 1:45 pm
This talk provides a broad, visionary perspective about the dynamic changes impacting electronic design automation tools and methodologies and their pivotal role in re-shaping engineering lifecycle management. It explains the trend toward convergence of EDA and CAE domains to address exploding system complexity and deliver multi-disciplinary solutions. Future workflows must incorporate digital threads that connect virtual prototypes and digital twins with physical systems. Predictive simulation and analysis across domains is key to accelerating engineering lifecycles.
Rapid industry adoption of AI, heterogeneous integrated circuits and chiplet technologies, software automation using scripting languages, and comprehensive data and intellectual property management tools is driving a seismic shift in design and verification methodologies. This talk covers how these EDA technologies contribute to more efficient and effective enterprise lifecycles. Application of these technologies must elevate RF, microwave, and mixed-signal design to an equal footing with digital design to achieve modernization of engineering workflows.
ABOUT: Niels Faché is responsible for Keysight’s design and simulation portfolio. In his most recent positions, he was Vice President and General Manager of the Remarketing Solutions Division and then the Keysight Services Portfolio Organization, both part of Keysight’s Global Services Organization (KGSO). Niels joined Hewlett Packard in 1994, when HP acquired Alphabit, a start-up software company in Belgium. He was co-founder and CEO of Alphabit, which developed the electromagnetic simulator Momentum - now part of the PathWave Advanced Design System (ADS). During his career, Niels has since held a variety of R&D, marketing, product planning and general management positions at HP, Agilent and Keysight in Electronic Design Automation, Test and Measurement Product Lines and Services. His roles have often involved leveraging technology and talented teams to transform and grow organizations into front-runners. He is based in Santa Clara, California. Niels holds a master’s degree and Ph.D. in electrical engineering, both from the University of Ghent, Belgium, where he also served as a part-time professor from 1995 to 1997. He has a business degree from the Université Libre de Bruxelles, Belgium, and has completed coursework at the Stanford Center for Professional Development.
AI Acceleration Roadmap: Co-designing Algorithms, Hardware, and Software
Wednesday, June 26 | 1:00 pm - 1:45 pm
Deep Neural Networks (DNNs) have become state-of-the-art in a variety of machine learning tasks spanning domains across vision, speech, and machine translation. Deep Learning (DL) achieves high accuracy in these tasks at the expense of 100s of ExaOps of computation. Hardware specialization and acceleration is a key enabler to improve operational efficiency of DNNs, in turn requiring synergistic cross-layer design across algorithms, hardware, and software.
In this talk I will present this holistic approach adopted in the design of a multi-TOPs AI hardware accelerator. Key advances in the AI algorithm/application-level exploiting approximate computing techniques enable deriving low-precision DNNs models that maintain the same level of accuracy. Hardware performance-aware design space exploration is critical during compilation to map DNNs with diverse computational characteristics systematically and optimally while preserving familiar programming and user interfaces. The opportunities to co-optimize the algorithms, hardware, and the software provides the roadmap to continue to deliver superior performance over the next decade.
ABOUT: Viji Srinivasan is a Distinguished Research Staff Member and a manager of the accelerator architectures and compilers group at the IBM T.J. Watson Research Center in Yorktown Heights. At IBM, she has worked on various aspects of data management including energy-efficient processor designs, microarchitecture of the memory hierarchies of large-scale servers, cache coherence management of symmetric multiprocessors, accelerators for data analytics applications and more recently end-to-end accelerator solutions for AI. Many of her research contributions have been incorporated into IBM’s Power & System-z Enterprise-class servers.