14.1 “Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware”

20.3 “BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits”

22.1 “State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System”

31.3 “MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction”

32.6 “Code Coverage of Assertions Using RTL Source Code Analysis”

33.1 “Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations”

43.2 “Physics-Based Electromigration Assessment for Power Grid Networks”

44.1 “On Trading Wear-Leveling with Heal-Leveling”

45.4 “Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side Channels”

56.1 “PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs”

64.6 “Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data”

65.1 “ePlace: Electrostatics Based Placement Using Nesterov's Method”

ESS
27.1 “Checkpoint Extensions for Simics SystemC VPs”
27.6 “End-to-End Personal Analytics System for User-friendly Query Processing”

BACK END
71.3 “Sign-off Correlation Methodology for Timing Optimization”
16.4 “Machine Learning Based High-Accurate Hotspot Detection with Boosting Algorithm”

FRONT END
38.5 “The Evil’s In The Edits”
38.2 “Less Is More: how we learned to avoid overconstraining”

ESS
301.29 “Application-Specific Hierarchical Power Management for Multicast High Efficiency Video Coding”

BACK END
302.5 “Which is the Best Multiple Patterning Process for Sub-10nm Technology Node?”
301.7 “Area gain in complex System-on-chips using Channel-less methodology”

FRONT END
301.57 “Power Intent Standards: Design, Interoperability and Anticipating the Future Improvements”