14.1 “An EDA Framework for Large Scale Hybrid Neuromorphic Computing Systems”
26.1 “DERA: Yet Another Differential Fault Attack on Cryptographic Devices Based on Error Rate Analysis”
27.1 “Battery Lifetime-Aware Automotive Climate Control for Electric Vehicles”
30.1 “Trends in Functional Verification: A 2014 Industry Study”
32.6 “Code Coverage of Assertions Using RTL Source Code Analysis”
35.1 “A Control-Theoretic Approach for Energy Efficient CPU-GPU Subsystem in Mobile Platforms”
39.1 “HAFIX: Hardware-Assisted Flow Integrity Extension”

1.4 “Techniques for Power and IR Drop Optimization in Sensor Digital IP”
15.3 “Why Testbench Should Control Processor Execution: “A Novel Approach to Bridge the Gap Between IP and SoC Verification”

6.3 “A Methodology to Analyze Edge-to-Edge Jitter for High Speed DDR Interfaces with PDN Noise”
6.5 “Design Methodology for Operating in Near-Threshold-Computing (NTC) Region”
38.2 “Next Generation Hybrid Clock Tree”
38.4 “Accelerating Productivity Using Design Automation for Low Skew Global Clock Distribution in a Complex SoC”

25.2 “SAE-Platform: A Platform for System Architecture Exploration”
25.6 “Automatic Generation & Integration Of Test Management Structure at SoC Level Using IP-XACT Methodology”
52.2 “RTL2RTL Formal Equivalence: Boosting the Design Confidence”
52.5 “Hierarchical Lint with Abstract Models: An Efficient, Practical and Scalable Flow for Billion Gate SoCs”

9.2 “Modeling Streaming Interfaces with Adaptive Accuracy Using TLM2”
9.6 “Architectural Exploration Platform for Solid State Drive Designs”
44.2 “Continuous Integration Build and Release Ingredients”
44.5 “System Simulator for High-Speed Link Design”