“Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing”

Lucas Deutschmann | TU Kaiserslautern
Johannes Mller | TU Kaiserslautern
Mohammad Rahmani Fadiheh | TU Kaiserslautern
Dominik Stoffel | TU Kaiserslautern
Wolfgang Kunz | TU Kaiserslautern

  • “BlueSeer: AI-Driven Environment Detection via BLE Scans”

  • “DeepGate: Learning Neural Representations of Logic Gates”

  • “Glimpse: Mathematical Embedding of Hardware Specification for Neural Compilation”

  • “Heuristic Adaptability to Input Dynamics for SpMM on GPUs”

  • “Domain Knowledge-Infused Deep Learning for Automated Analog/RF Circuit Parameter Optimization”

“Robust UVM framework for detection of hardware security vulnerabilities for security sub systems and cryptographic IPs”

Niharika Sachdeva, Arjun Kumar, Somasunder KS and Anil Deshpande | Samsung Semiconductor

“Verifying Register Maps with JasperGold: How Formal compares to UVM”

Davide Sanalitro & Edoardo Bollea | STMicroelectronics
Maurizio Martina & Guido Masera | Polytechnic University of Turin
Hsiu Tsai | Global UniChip Corp.

“Experimental Validation of a Novel Methodology for Electromigration Assessment in On-chip Power Grids”

Valeriy Sukharev | Siemens EDA

“Power Aware Scan Structure Planner”

Chen Yuan Kao, Sin Huei Li, Chien Chen Wu, Min Hsiu Tsai | Global UniChip Corp.

“Design for Manufacturability (DFM) for Analog IP”

Sylvain Guilley | Secure-IC
Lynn Wang | GlobalFoundries

“Automatic Checkpoint Support in the Device Modeling Language (DML)”

Jakob Engblom | Intel Corporation