My first job was as a chip designer at TRW, Sunnyvale back in the 1980s. We had our own fab in Virginia, and my officemate wrote and maintained our chip design tools, as was pretty typical in those days. I worked at a series of hardware startups after that; and then took all that experience in hand to build better chip design tools. At Chronologic I led the engineering team that built the VCS simulator; then I started Surefire, where we built the SureCov and SureLint verification tools; we merged with Verisity and then into Cadence, where my team developed C-to-Silicon synthesis tools. If you’re curious, LinkedIn has most of the rest of the story, including the patents I've been issued.
When I started out, a big chip had 3,000 gates and needed a team of five or six people to get it right. Today it’s not uncommon for one designer to be responsible for millions of gates, and work in a team that spans the globe, all thanks to the increasing power of the EDA tools our industry built. Every year at DAC new tools and enhancements are introduced which make the chip design process more predictable, increase its capacity, and basically enable the same human to do twice as much design as they could previously. Indeed this inexorable productivity increase is one reason DAC’s attendance has waned through the years. In some ways, we’re the victim of our own success, though I must point out that attendance was up last year — dramatically so in the case of the technical conference!
The organizers of DAC has evolved and expanded its focus over the years, always following the ‘cutting edge’ of the new design challenges; the possibilities made real by new design nodes, design tools and methodologies. Here’s one example: We’ve pretty much perfected design techniques for designing and verifying processors, memories and FPGAs at the current nodes. However the methodologies and tools for building and verifying devices with tens to hundreds of sensors, all internet-connected, ultra-low power and extremely secure, are in their infancy. Big challenges remain when it comes to power/batteries, security and more, a big reason DAC is now loaded with IoT-related technical presentations and exhibits.
We continue to embrace other domains at the cutting-edge of design automation, including embedded systems and software, automotive, IP and security. This expansion of our focus continues even as we remain the premiere conference for our core EDA track, spanning design to verification; synthesis to place and route; and implementation to post-silicon.
A big part of DAC’s value is that it is really four events in one — the Exhibit Hall is our industry’s premier showcase of tool and technology vendors; the Research track features work from the cutting edge of academia and corporate R&D, and the Designer and IP tracks feature a wealth of hands-on information from practitioners around the world.
Pulling this all together over the next several months is a big task; and the way I’ve accomplished big things in the past is by getting together group of great people, from the executive committee on down, and giving them the tools they need to get the job done. I’m privileged to work with some of the most dynamic and experienced people in our industry, many of whom, like me, have served in some capacity at DAC for years, along the way developing a deep affection for the conference, the industry and our ecosystem. I’m looking forward to introducing some of my fellow executive committee members over the next few months, but for now, check out the all-star lineup here.
With their help, and yours, it’s going to be a great #54DAC.