Which made me ponder…what do you believe is lurking in the deep submicron below 10nm? We’ve already uncovered so much as we’ve descended down the technology nodes — the rise of systematic defects as the primary cause of yield failures, the delay in EUV driving the need for multi-patterning technology, the introduction of new geometries in finFET transistors and 2.5/3D constructions, and the integration of traditional CMOS with new technologies such as MEMs and silicon photonics. What haven’t we discovered yet?
And where do you go to find out? Well, now we get around to DAC. You will attend DAC, right? I’m sure there will be enough content in the technical and vendor programs to keep you busy, educated and entertained. Better yet, submit a paper, tutorial, workshop or panel idea to talk about your work in deep submicron (and the other areas we cover at DAC). The call for contributions will be live on the website on September 15th, so mark your calendar now. Join your peers around the industry in diving deep into some of the most compelling topics in EDA and beyond.