In one of those odd coincidences, I was having dinner with a friend last week and somehow the Carrington Event came up. Then I read a a piece in EETimes about whether electrical storms could cause problems in the near future. Even that piece didn't mention the Carrington Event so I guess George Leopold, the author, hasn't heard of it.
It constantly surprises me that people in electronics have not heard of the Carrington Event, the solar storm of 1859. In fact my dinner companion (also... Read More
In the last few decades, electronics has become more and more central to our lives. When I was a child the only electronics in the house was the radio and the television, both of which contained tubes. Two big things happened that upended that world: the invention of the transistor and the invention of the integrated circuit. A modern integrated circuit, or chip as some people like to call them, may have over a billion transistors on it and yet sell for just a few dollars. Perhaps more... Read More
I don't usually cover company white papers here. There are too many companies who attend DAC to cover everything they say. But occsionally something comes along which is interesting enough to call out. Cadence has a white paper on 20nm design. It's not a Cadence sales pitch and doesn't even mention Cadence products. Everyone who is interested in the various new things about 20nm design should read it and will probably learn stuff. It's all about the problems, and, in the most generic way, the... Read More
For the first time ever the EDA industry has a $1.75B company. Synopsys announced their results today. Revenue was $444M and their guidance for their whole fiscal year (which ends at the end of October, trick or treat) is $1.742B to $1.75B. I think Cadence got to about $1.5B around 2000 before the first of two major resets which have taken them from #1 to #3. At that time, Synopsys were $780M so roughly half Cadence's size. Mentor has also grown significantly over the years and was over $1B... Read More
At Semicon, Ben Rathsack of Tokyo Electron America talked about directed self assembly (DSA) at the standing-room only lithography morning. So what is it? Self assembly involves taking two monomers that don't mix and letting them polymerise (so like styrene forming polystyrene). Since they won't mix they will form up into separate areas for the two polymers. If you do nothing else you will end up with somewhat random patterns like a fingerprint. But if you provide guides, either physical... Read More
At DAC each year, CEDA (IEEE Council on Electronic Design Automation) sponsors a distinguished speaker over Tuesday lunch. This year it was Mark Horowitz talking about Digital-Analog Design. Dr Horowitz is chairman of Stanford Universities Electrical Engineering Department. The focus of his talk was on how analog design tools have not progressed much over the recent decades in the same way that digital design tools have done. The heart of digital design has been the creation of effective... Read More
There's a dirty secret problem about EUV that people don't seem to to be talking about. There's no pellicle on a EUV mask. OK, probably you have no idea what that means, a lot of jargon words, nor why it would be important, but it seems to me it could be the killer problem for EUV.
In refractive masks, you print a pattern on a plate of quartz. Then you cover it with another layer known as the pellicle (I speak French and that is the name for film in the pre-digital era camera, but it... Read More
This is really the second part to my blog about the challenges of EUV lithography. The next speaker was Franklin Kalk who is CTO of Toppan Photomasks. He too emphasized that we can make almost arbitrarily small features but more and more masks are required (not, that I suspect, he would complain being in the mask business). For EUV to go mainstream the costs must be lower than this and the masks must be defect-free enough. This may happen earlier in memory since the existing built-in... Read More
EUV is the great hope for avoiding having to go to triple (and more) patterning if we have to stick with 193nm light. There were several presentations at Semicon about the status of EUV. Here I'll discuss the issues with EUV lithography and in a separate post discuss the issues about making masks for EUV. It is probably worth being explicit and pointing out that the big advantage of EUV, if and when it works, is it is single patterning technology (for the forseeable future) with just... Read More
EDAC announced that EDA industry revenue increased 6.3% for Q1 2012 to $1536.9M compared to a year ago. Sequentiallly it declined, as it normally does from Q4 to Q1, by 9.6%. Every category except services increased revenue and every region increased revenue except for Japan. The full report is available by subscription, of course.
Here are a few highlights:
CAE up 6.5% to $564.8M
IC Physical Design and Verification up 10.2% to $350.9M
PCB up 5.1% to $147.5M
IP up 5.4% to $391.3M
Services,... Read More
I wrote here about the EDAC Emerging Companies panel with Jim Hogan that took place at Silicon Valley Bank.
The next event in the series will take place on October 17th. The topic is not yet announced but "save the date". Just like last time, reception at 6pm, the panel at 7pm and it should all wrap up around 8.30pm or so. Note that this time it is at Cadence. I'm assuming in building 5 since that is where things like this usually take place at Cadence. And Cadence is at 2655 Seely Avenue in... Read More
One of the presenters at the standing-room only litho session at Semicon this week was Serge Tedesco, the litho program manager at CEA-Leti in Grenoble France. He is running a program called IMAGINE for maskless lithography. Chips today are built using a reticle (containing the pattern for that layer of the chip) which is exposed one die at a time with a flash of light, and then the wafer is moved to the next die and the process is repeated. The nice thing about this process is that the... Read More
I have been spending some time at Semicon West at the Moscone center the last couple of days. The big news of the show was Intel/ASML's announcement that Intel is putting a lot of money into ASML for EUV (see below) and 45cm (18") wafer technology. They were even one of the speakers at a fascinating session I attended. I spent all morning at a series of presentations about lithography. I blogged recently about how wafer prices going up faster than transistor densities (the scariest... Read More
Writing the DAC blog it is hard to know what rules make sense as to what to allow or not allow myself to write about. There are a couple of hundred companies at DAC, half a dozen quite large companies, and maybe a thousand product announcements each year. So one easy decision is not to cover product announcements at all. But sometimes news from the large companies is significant and worth covering because it is of general interest. I was travelling when the promotion of Chi-Foon Chan to co-CEO... Read More
Everyone knows Moore's Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.
But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in... Read More