Cadence has brought a suit against Berkeley Design Automation for, as far as I can see, integrating their AFS circuit simulator with the Virtuoso Analog Design Environment (ADE) without using the (licensed) Oasis product. Since BDA is (actually was) a member of the Cadence Connections program, they have to abide by the contract which only allows them to create interfaces that their Connections legal contract allows. In particular "Member is not licensed to develop any interface to or... Read More
UBM's EETimes and EDN today announced Kathryn Kranen as the lifetime achievement award winner for this years ACE awards program. Kathryn, of course, is the CEO of Jasper (and is also currently the chairman of EDAC). Past winners exemplify the prestige and significance of the award. Since 2005 the award was given to Gordon Moore, then the Chairman emeritus of Intel, Wilf Corrigan, the Chairman of the board of LSI, Chung-Mou Chang the Founding Chairman of TSMC and Pasquale Pistorio the... Read More
This year's recipient of the Kaufman Award is Dr Chenming Hu. I can't think of a more deserving recipient. He is the father of the FinFET transistor which is clearly the most revolutionary thing to come along in semiconductor for a long time. Of course he wasn't working alone but he was the leader of the team at UC Berkeley that developed the key structures that keep power under control and so allow us to continue to scale process nodes. In the past, the Kaufman Award recipient has been... Read More
The program for EDPS in Monterey this April 18th and 19th is now available.
The first day has a keynote by Ivo Bolsens, the CTO of Xilinx, on The All Programmable SoC - At the Heart of Next Generation Embedded System. That is followed by 3 sessions on ESL & Platform, Design Collaboration, and 3D-IC.
The second day has a keynote by Daniel Nenni on The FinFET Value Proposition. This is followed by two sessions, also on FinFET. FinFET Design Challenges, and FinFET Design Enablement Challenges... Read More
The entire program for DAC is now live here. Registration is now open here. It is just a little over two months to go. I'll blog later about some of the special sessions and tracks at this years DAC, some because it is looking back over the last 50 years and some because it is in Austin for the first time. But go and sign up (exhibitor registration is also open).
Somebody pointed out this fascinating teardown (sorry, can't remember who it was. Oops). It is a teardown of a 1986 Psion II organiser, a 1996 Palm Pilot 5000 (back when they were still US robotics and before Pilot pens made them drop the Pilot name) and then an HP iPaq 5550. It is interesting to watch the level of integration increase and the density of the circuit boards really go down as IC packaging technology changes (these are all QFP chips I think). It is amazing how much stuff we... Read More
Mike Demler has an interesting article using the 50th DAC (or, as he pedantically points out, the 49th anniversary of the first DAC) as a reason to look back at what are the most significant development in the history of EDA. GDS, Spice, HDL. Go read the whole article to find out his other choices.
I just recently blogged about the CEO panel which had Simon Segars of ARM on it. He was sort of an impostor since he wasn't actually the CEO of ARM. But that is all about to change. ARM announced yesterday that Warren East, the CEO, would be retiring at the end of June. The new CEO will be Simon, currently President of ARM and the de facto #2 guy. Currently Simon is based in the US and I don't know if he plans to return to Britain or not. But he will live what will inevitably be a lifestyle... Read More
Yesterday evening was the annual EDAC CEO forecast meeting. Actually it is not really a forecast meeting any more, more a sort of CEO response to some survey questions asked of EDAC members. Rich Valera of Needham moderated with Lip-Bu, Aart and Wally, along with Simon Segars representing the IP arm of the business and Raul Camposano representing startup companies.
I’m not going to try and cover everything, just pick and choose things that I found interesting.
The first question asked was... Read More
EDAC's next Hogan Emerging companies features Joe Costello on the subject of Communicating a Compelling Company Story. It is May 1st at (surprise) Cadence. Anyone who saw Joe's DAC keynote on a similar topic a few years ago will never forget it. The event is sure to sell out so register as soon as you can. Details, including a link to registration, are here.
For 20 years (it is an anniversary year this year, have you noticed it's DAC's 50th anniversary) there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey. This year it is Thursday and Friday April 18th/19th.
The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC -- at the Heart of Next-Generation Embedded Systems. The morning is then devoted to system and platform design,... Read More
Next week is EDAC's annual CEO forecast panel. It is in the Doubletree in San Jose. The big guys are all here this year, Aart, Wally and Lip-Bu (isn't it great that in EDA all the CEOs just need a first name since none of them are called John or something more common). Simon Segars of ARM (not the CEO but indeed the President of ARM). This year's token startup CEO is a heavy hitter: Raul Camposano, currently CEO of Nimbic but for many years CTO (and other positions) at Synopsys. Richard Valera... Read More
I used my secret powers (being a blogger will get you a press pass) to go to the first day of the SPIE conference on advanced lithography a couple of weeks ago. Everything that happens to with process nodes seems to be driven by lithography, and everything that happens in EDA is driven by semiconductor process. It is the place to find out if people believe EUV is going to be real (lots of doubt), how about e-beam, is directed self-assembly really a thing.
The keynote was by William Siegle... Read More
The most interesting session at the Linley Tech Data Center Conference last month was the last one, on Designing Power Efficient Servers. What this was really about was whether ARM would have any success in the server market and what Intel's response might be. This is something of importance to the whole semiconductor ecosystem since, at heart, it is also about IDM versus foundry. And with Altera announcing that it would be using Intel as a foundry at 14nm the world is changing.
Datacenters are... Read More
At the Common Platform Technology Forum there were a number of presentations by people from IBM about Silicon and Carbon Nanowires/tubes.
So what is a silicon nanowire? It is basically a FET where the active element is a wire 3-20nm in diameter. So where a FinFET has the gate wrapped around 3 sides of the transistor, a nanowire (NW) has it wrapped around all four. In essence, the wire runs through the middle of the gate.
There seem to be three issues about building a silicon nanowire.... Read More