12.1 Accurate Phase-Level Cross-Platform Power and Performance Estimation
13.2 Correlated Bayesian Model Fusion: Efficient Performance Modeling of Large-Scale Tunable Analog/RF Integrated Circuits
14.4 Designing Approximate Circuits using Clock Overgating
21.1 A New Learning Method for Inference Accuracy, Core Occupation, and Performance Co-optimization on TrueNorth Chip
22.2 Design Partitioning for Large-Scale Equivalence Checking and Functional Correction
23.3 Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors
29.3 Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling
30.1 Multiple Patterning Layout Decomposition Considering Complex Coloring Rules
31.2 Improving Mobile Gaming Performance through Cooperative CPU-GPU Thermal Management
39.1 Distributed On-chip Voltage Regulation: Theoretical Stability Foundation, Over-design Reduction and Performance Optimization
40.3 EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
41.2 Improving Performance and Lifetime of NAND Storage Systems Using Relaxed Program Sequence
48.4 A Novel Cross-Layer Framework for Early-Stage Power Delivery and Architecture Co-Exploration
49.1 A High-resolution Side-Channel Attack on Last Level Cache
56.4 Legalization Algorithm for Multiple-Row Height Standard Cell Design
58.1 Enabling Sub-blocks Erase Management to Boost the Performance of 3D NAND Flash Memory
All presentations will be considered for the Best Presentation Award.
DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP).
DAC 2018 will be held in San Francisco, California at Moscone Center West. Get details about travel, hotels, and area attractions in one convenient spot.
