ALAMEDA, CALIF. –– May 11, 2016 –– Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers, today announced that two of its longtime customers joined a growing list of other customers who have achieved successful exits through acquisitions.
Yogitech, a leading provider of services and solutions for functional safety, was acquired by Intel Corporation, while Rocketick Technologies Ltd., a leading provider of simulation acceleration solutions for chip verification, is now part of Cadence Design Systems. They follow other highly successful Verific licensees including, Denali, Forte and Jasper Design Automation who were acquired by Cadence. Synopsys purchased Atrenta and EVE, while Mentor Graphics bought Calypto and Oasys.
“We’ve had remarkably strong relationships with both Rocketick and Yogitech and take a measure of pride in their accomplishments,” remarks Michiel Ligthart, Verific’s president and chief operating officer. “We wish them well as they move into larger, more established companies, and look forward to the same type of relationships with Intel and Cadence.”
Both companies integrated Verific’s parsers into their respective software that are in production and development flows. Rocketick, a Verific customer since 2009, adopted Verific’s SystemVerilog parser as the front end to RocketSim™, a multi-core processor-based accelerator used on a wide range of Verilog simulations to solve functional verification bottlenecks.
Yogitech selected Verific’s Verilog and VHDL parsers to work with faultRobust Technology, its functional safety analysis and safety-oriented design exploration software.
Verific invites attendees to view demonstrations of its parsers in Booth #538 during the Design Automation Conference (DAC) and to pick up this year’s giraffe giveaway. DAC will be held June 5-9 between10 a.m. and 6 p.m. at the Austin Convention Center in Austin, Texas. Contact Rick Carlson, Verific’s vice president of sales, to schedule a demonstration. He can be reached at (970) 948-9650 or via email at firstname.lastname@example.org or visit Verific’s website located at: http://www.verific.com
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: email@example.com Website: www.verific.com
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