Designer, IP Track Poster Session to Feature "Secure System Design With Tortuga Logic's Prospect”
SAN DIEGO, CALIF. –– May 27, 2014
WHO: Tortuga Logic, transforming the way hardware designers and system architects test the security of hardware designs
WHAT: Will demonstrate its comprehensive Prospect Hardware Security Design and Analysis Toolkit at the 52nd Design Automation Conference (DAC) in the OneSpin Solutions booth (#3126)
WHEN: Monday, June 8, through Wednesday, June 10
WHERE: Moscone Center, San Francisco
Tortuga Logic’s Dr. Jason Oberg will participate in the Designer and IP Track Poster Session, discussing “Secure System Design with Tortuga Logic”s Prospect,” Tuesday, June 9, from 4:30 p.m. until 6 p.m. on the DAC Exhibit Floor.
More information about DAC can be...
WILSONVILLE, Ore., May 27, 2015
The Veloce® Power Application Software delivers:
• A complete solution that enables a new comprehensive methodology for power
-Accurate and early switching activity at the application level
-Early budgeting and tradeoff exploration at RTL
-Analysis and sign off at the gate level
• Real-time transfer of power switching activity, via a Dynamic Read Waveform API, to power analysis tools replacing current file-based activity transfer methodology
• Tight integration with an ecosystem of industry-recognized power analysis tools
For a technical whitepaper visit: http://www.mentor.com/products/fv/techpubs/download/?id=90538
Mentor Graphics Corporation (NASDAQ: MENT) today released the Veloce® Power Application...
So-ADE Debugger Developed to be Easy to Use, Intuitive
SAINT GEOIRE EN VALDAINE, FRANCE –– May 21, 2015 –– So-ADE™ today announced immediate availability of an easy-to-use and intuitive debugger for the development and debugging of the SystemVerilog, VHDL and UPF parser platform from Verific Design Automation.
Meant for C/C++ developers, So-ADE adds electronic design automation (EDA) concept knowledge to the debugger level. It automatically manipulates the Abstract Syntax Tree (AST) from VHDL, Verilog or SystemVerilog hardware description languages, parsing for faster code development and algorithm debug with commonly used data structures.
“We’re delighted that So-ADE created a product around our parser platform, and they have our full support,” notes...
Apps Model Adopted by OneSpin Solutions, Tortuga Logic to Link Formal Verification Platform with Hardware Security Design and Analysis Toolkit
SAN DIEGO and SAN JOSE, CALIF. –– May 21, 2015 –– OneSpin Solutions™ and Tortuga Logic today signed a multi-year original equipment manufacturer (OEM) agreement, enabling Tortuga to integrate OneSpin 360 LaunchPad™, OneSpin’s new adaptive formal platform, with Prospect, its Hardware Security Design and Analysis Toolkit.
LaunchPad, introduced today by OneSpin Solutions, offers a way for third-party suppliers such as Tortuga Logic to embed its formal verification software into their products or “apps.” (See separate news release titled “OneSpin Solutions Catalyzes Unique, Third-Party Verification Solutions by Delivering OneSpin...
Advanced Formal Verification Technology Platform from OneSpin Used by Partner Companies in Range of New, Unique Verification Solutions
SAN JOSE, CALIF. –– May 21, 2015 –– OneSpin Solutions™, provider of innovative formal solutions targeting a broad range of challenging verification problems, today unveiled 360 LaunchPad™, an adaptive formal technology platform that allows third-party companies with limited knowledge of formal technology to develop and deliver formal-based apps.
LaunchPad is a complete formal environment that can be utilized by app developers without in-house formal technology or expertize. It allows domain experts to efficiently create formal-based solutions targeting their field on a proven underlying verification foundation. LaunchPad may be delivered as...
Apps Model Links Formal Verification Platform to Automatic Register Verification Software
LOWELL, MASS., and SAN JOSE, CALIF. –– May 21, 2015 –– OneSpin Solutions™ and Agnisys, Inc., today signed a multi-year original equipment manufacturer (OEM) agreement, whereby Agnisys will integrate OneSpin’s LaunchPad™, OneSpin’s new adaptive formal platform, into its ARV-Formal™ automatic register verification software.
Introduced today by OneSpin Solutions, LaunchPad gives third-party suppliers a way to embed its formal verification software into their products, or “apps.” (See separate news release titled “OneSpin Solutions Catalyzes Unique, Third-Party Verification Solutions by Delivering OneSpin 360 LaunchPad, First Adaptive Formal Platform.”)
Agnisys, under terms of the...
NanoSpice Giga Replaces FastSPICE in Memory Design and Verification Flow
SAN JOSE, CALIF. –– May 19, 2015 –– ProPlus Design Solutions, Inc. today announced Attopsemi Technology Co., of Hsinchu, Taiwan, developer of state-of-art logic-compatible one-time-programmable (OTP) memory intellectual property (IP), has adopted its high-capacity, high-performance parallel GigaSpice simulator for giga-scale circuit simulation.
Attopsemi replaced its existing FastSPICE simulator in its design and verification flow with ProPlus’ NanoSpice Giga™ because of its highly accurate and superior performance.
“Since our founding in 2010, we have been on a mission to provide the best logic-compatible OTP IP for SoC integrations from 0.7um to 7nm CMOS that’s smaller, higher...
New Accurate Model, 10 Systems Available on Carbon’s IP Exchange Web Portal for Download, Broadening Carbon’s Range of Accurate Solutions
ACTON, MASS. –– May 19, 2015 –– Carbon Design Systems, Inc., the leading supplier of accurate virtual prototype solutions, announced today immediate availability of multiple Carbon Performance Analysis Kits (CPAKs) featuring the ARM® Cortex®-A72 processor core.
In addition, designers can now configure their own implementation accurate virtual model of the Cortex-A72 on Carbon’s IP Exchange web portal.
“Our growing portfolio of CPAKs and the new Cortex-A72 virtual model offers designers a wide range of accurate solutions easily downloadable from our system and IP web portals,” notes Bill Neifert, Carbon’s chief...
Moves Signal Next Phase of Oski’s Growth
MOUNTAIN VIEW, CALIF. –– May 19, 2015 –– Oski Technology, Inc., the only dedicated formal verification service provider, today appointed Amit Joshi to the position of vice president of engineering. He will work from the Oski Technology office in Gurgaon, Haryana, India.
In a related move, Jin Zhang has been promoted to vice president of marketing and customer relations. Both report to Vigyan Singhal, Oski’s president and chief executive officer.
“It gives me great pleasure to announce these appointments,” says Singhal. “Amit has had a storied career managing both projects and engineering teams, and will be an asset to us, while Jin has proven to be an adept marketing executive who has kept Oski visible. As the...
Chandler, Arizona – May 13, 2015. Originally designed to be a fully automatic analog IC block creator/migrator, Get2Spec / Analog Rails extended their offering to be the complete IC open access design platform, which now includes an intgrated digital solution, design management, and a one man day process set up.
With this new release, all aspects of the IC design flow is built in, including digital place and route with timing optimization, automatic standard cell generators and characterization, design management configurable to commit to/from 3rd party repositories, and a one man day PDK cockpit.
Created by circuit designers for circuit designers, Analog/Digital Rails integrates schematic, layout, simulation, optimization, sensitivity, automatic placers and...