Recognizes Technical Excellence at
Annual SNUG San Jose Conference
Twentieth Anniversary Celebration
and Expanded Technical Track Program
among the Highlights at EDA’s
Largest Users Group
MOUNTAIN VIEW, Calif., April 12, 2010
-- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for
semiconductor design, verification and manufacturing, today announced the Best Paper Awards for the
twentieth annual Synopsys Users’ Group (SNUG®) San Jose conference, held in
Santa Clara, Calif. on March 29-31. First place was awarded to Alvin
Loke, Dru Cabler, Chad Lackey, Tin Tin Wee and Bruce Doyle of AMD and Zhi-Yuan
Wu of GLOBALFOUNDRIES for
“Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale
CMOS Analog Design”; Alvin
Loke won the Best First-time...
Companies Select Broad Portfolio of High-Quality DesignWare IP as Preferred Solution for SoC Designs
MOUNTAIN VIEW, Calif. – April 14, 2010 —Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that eSilicon and Brite Semiconductor have joined the Synopsys IP OEM Partner Program along with renewed members Global Unichip and Open-Silicon. Through the IP OEM Partner Program, members standardize on Synopsys’ broad portfolio of silicon-proven DesignWare® interface and analog IP such as USB, PCI Express®, DDR, HDMI, SATA, Ethernet, MIPI IP including 3GDigRF, CSI-2, D-PHY, data converters and audio codecs for their system-on-chip (SoC) designs. By enabling member companies to access a...
Real Intent Releases Ascent Lint Version 1.2
Offering New Rule Support with Low-Noise and High-Performance Linting
SAN JOSE, California – January 19, 2010 - Real Intent Inc., the innovator in automating the intelligence of formal techniques for design verification, announced today that it is shipping Ascent™ Lint Version 1.2.
Ascent Lint is the next generation lint tool in the Ascent early functional verification family of products. It performs syntax and semantic Lint checks for today’s complex SoC designs. Ascent Lint 1.2 now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise. These rules cover the following areas:
Shalom Bresticker Receives Accellera’s 2010 Technical Excellence Award
Award recognizes efforts to improve quality of Verilog, SystemVerilog and Verilog AMS standards
NAPA, Calif., February 23, 2010 — Accellera, the electronics industry organization focused on electronic design automation (EDA) and Intellectual Property (IP) standards, announced today that Shalom Bresticker, Senior CAD Engineer, Intel, is the 2010 recipient of its 7th annual Technical Excellence Award. The Award recognizes Mr. Bresticker’s volunteer contributions to Accellera’s SystemVerilog, Open Verification Library (OVL) and Verilog Analog/Mixed Signal (AMS) standards.
Accellera’s chair, Shrenik Mehta, will present Accellera’s Technical Excellence Award at 3pm on Wednesday, February 24, 2010, during...
IEEE Approves Four Accellera and SPIRIT Consortium Standards in 2009
Total sets one-year ratification record
PISCATAWAY, N.J., and NAPA, California, USA, 16 February 2010 -- The IEEE, Accellera and The SPIRIT Consortium, announced today that the IEEE has approved a record number of Accellera and The SPIRIT Consortium Electronic Design Automation (EDA) and Intellectual Property (IP) standards in 2009.
The recently approved IEEE standards are:
Accellera’s SystemVerilog standard, ratified in November as IEEE 1800™-2009, the SystemVerilog-Unified Hardware Design, Specification, and Verification Language Standard
The SPIRIT Consortium’s IP-XACT standard, ratified in December as IEEE 1685™ IP-XACT-2009, a Standard Structure for Packaging, Integrating and Re-Using IP...
SiPArray™ integrated passives technology combined with HiPer Silicon™ software provides breakthrough for complete A/MS IC design solution
MONROVIA, California and BURLINGTON, Ontario, Canada -- February 16, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and Sound Design Technologies (SDT), a leading designer and manufacturer of integrated passives and stacked-die assemblies, are collaborating to develop process design kits (PDKs) for analog/mixed-signal (A/MS) designers using Tanner EDA’s HiPer Silicon™ software. This collaboration gives Tanner EDA customers access to SDT’s innovative SiPArrayTM integrated passives technology and SDT customers access to Tanner EDA’s A/MS tools for a...
Laker Custom Layout Automation System offers standard interoperability, robust ecosystem, and IPL support on proven foundation of unique automation
SAN JOSE, Calif., February 22, 2010– SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today announced the availability of its latest version of the Laker™ Custom Layout Automation System, which offers the industry’s most complete and robust support of the OpenAccess (OA) database standard. The release builds on several years of collaboration by SpringSoft with other industry leaders to develop the infrastructure and technology required to deliver on the promise of the OA effort.
The latest release of the Laker system is completely compatible with the OA database and API, which can be used as the center...
New Verdi Power-aware Debug Module enables visualization of power intent with RTL and UPF/CPF for automated debug and analysis
HSINCHU, Taiwan, February 8, 2010 — SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today introduced a new power-aware debug module for its award-winning Verdi™ Automated Debug System. Power-aware debug accelerates the comprehension of power intent and automates the process of visualizing, tracing and analyzing the source of power-related errors. The module is fully integrated with the hardware description language (HDL) debug capabilities of the Verdi system, the cornerstone of SpringSoft’s family of Novas™ Verification Enhancement products that enable engineers to do more verification in less time....
Continued improvement in quality of results and enhanced support for Xilinx DSP functions.
MOUNTAIN VIEW, Calif. -- January 28, 2010 – Synfora, Inc., the premier provider of high level synthesis tools for integrated circuit and system designers of complex processing applications, has released version 9.04 of its PICO Extreme™ and PICO Extreme FPGA C synthesis tools with enhanced support for C++ language constructs and new support for additional FPGA devices.
The PICO Extreme product line now offers additional C++ support, including support for classes, templates, and operator over-loading; host interface and memory mapping enhancements, including flexible address mapping; and enhanced language support, with expanded support for looping syntax and expanded pointer support.
Synthesis of untimed C algorithms shows quality of results comparable to hand coding
MOUNTAIN VIEW, Calif. – February 1, 2010 – Synfora, Inc., the premier provider of high level synthesis tools for integrated circuit and system designers of large, complex processing applications, today announced that Bosch Security Systems has selected PICO C Synthesis tool for FPGA development as its C Synthesis solution to accelerate the prototyping and synthesis of C algorithms in product development. Bosch Security Systems has an extensive portfolio of innovative, high-quality, ergonomic products and systems for security, safety and communications. Using PICO C Synthesis for FPGA allows Bosch Security Systems to reduce design and verification time and cost while getting product to market more...