In the early 2000s we hit a power "wall" and decided to scale it by putting multiple processor cores on a single chip. But the multi-core era is running into limitations, and it's time to start planning for a "new era" in which design innovation will fuel performance growth, according to Design Automation Conference (DAC 2012) keynote speaker Joshua Friedrich (right), senior manager of POWER technology development in IBM's Server and Technology Group.
Friedrich gave the first part of a two-speaker keynote titled "Designing High Performance Systems-on-Chip" June 6. Brad Heaney, Intel Architecture group product manager, gave the second part, which showed how Intel developed the 3rd Generation Intel Core Processor (code named Ivy Bridge). Both...
This year’s Design Automation Conference, recently held in San Francisco, CA, highlighted many advances in analog and digital circuit design tools, but in the analog and mixed-signal world many designers are hesitant to give up tried and true manual design techniques to implement their circuits. They feel analog design is still more of an art than a science and that most of the available tools can’t really come close to what a good analog designer can do. However, after hearing the pitches from several new and existing vendors of analog and mixed-signal design tools at this year’s DAC, I suspect many analog designers will be tempted to adopt some of the new tools to improve their productivity.
Although the major EDA tool suppliers–Cadence, Mentor and Synopsys...
DAC may be over, but the feeling of community and a job well done has stayed with those of us who staffed the EVE booth. We are quite happy with the turnout this year and, if you walked by our booth, you’ll know why –– our presentations were well attended all three days. Monday, in particular, was brimming with attendees all eager to learn more about our ZeBu hardware-assisted verification platform. In fact, we scheduled an additional presentation or two due to the heavy traffic and high degree of interest.
ZeBu’s new Post-run Debug (PRD) capability, a way to ensure that verification engineers never miss capturing a bug, created a lot of excitement, as did our low-power verification to check functional integrity of multi-power domains or islands on/off...
Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs. Get it wrong and/or miss a bug in the bypass logic and whole system can simply freeze.
Fortunately, the 2012 DAC User Track Best Presentation award-winning paper titled "Deploying Model Checking for Bypass Verification" by engineers from Cisco and Oski Technology (full citation below) describes an easily replicated, nearly push-button flow that does not require users to put in a lot of effort to write complex input constraints. And full disclosure: they used my favorite combined simulation+formal tool, Incisive Enterprise Verifier (IEV)!
There are three reasons why DAC will be spectacular come June in Austin: It’s the 50th instantiation of the conference; for the first time ever DAC is coming to the home of Office Space; and Synopsys Solutions Group Chief Architect Yervant Zorian will be General Chair, which means the 2013 Design Automation Conference has got the very best in the business at the top, a guy who’s CV includes leading committees of all shapes and sizes, IEEE Standards initiatives, and a variety of conferences, big and small.
Full Article - Peggy Aycinena, EDACafe
Aspera develops software transfer technologies to achieve performance and cost savings using existing network infrastructure. They also provide engineering services to implement their products and transfer technology in small to large business enterprises. I expect them to be showing how they can help multinational engineering teams to share design data and keep track of all it in a globally distributed environment.
ChipStart is an IP developer focusing on solutions such as SoC System Manager (SSM); custom embedded Memory products; and Voltage Regulators. They are also an IP Aggregator. They have IP partners working with them to create a larger potential for pre-integrated IP.
DXCorr Designs is focused on providing embedded solutions for foundation IP,...
Several weeks ago, I asked companies to send me information about the demos that would be showing at DAC this year. I am pleased to say that many companies responded. I hope you find this better than another list of what you must see at DAC, instead, you can be guided by some real information that may actually be helpful in planning your trip around the show floor. Companies that did not get information to me, feel free to add your information by placing a comment on this article.
Gary Smith, the dean of EDA analysts, has his sights set on two major trends he thinks will be prominent at this year's Design Automation Conference.
"The big thing at DAC this year is debug," said Smith, chief analyst at his own eponymously named firm, Gary Smith EDA. "We are debugging everything now."
Smith, who will be kicking off his 19th DAC with his annual state of EDA update on Sunday (June 3) at 7 p.m. at the Marriott Hotel in San Francisco, counts seven vendors offering some form of debug: EVE, Cadence, Mentor, SpringSoft, Axiom, Vennsa and IC Manage. "That is the hottest thing at DAC," Smith said.
Breaking your products so your customers won't have to.
Thoughts on hardware verification, the EDA industry, and related topics from the perspective of JL Gray, a verification consultant at Verilab.49th DAC: Day 1 Highlights
The 49th Design Automation Conference kicked off yesterday evening with a reception and a presentation by Gary Smith. One of the themes of Gary's talk was his observation that a phenomenon he termed "multi-platform design" was allowing chips to be designed for approximately $40M, as opposed to the $75M he had predicted last year. Part of the reason for the reduction in cost was, in his view, based on a significantly increasing use of ESL techniques (especially on the modeling and verification side of things...
Despite several glitches along the way, the semiconductor industry has managed to move down the process technology curve as defined by Moore’s Law. But going forward, the industry will require new breakthroughs in chip-scaling and EDA technology to enable the next wave of systems over the next decade, according to a technologist from ARM Ltd.
During and after a keynote address at the Design Automation Conference (DAC) in San Francisco on Tuesday (June 5), Mike Muller, chief technology officer at ARM, also addressed a range of other topics, including the state of the foundry industry, the demise of PCs, and, of course, the mobile revolution based on ARM’s technology.