The Designer Track brings together IC designers and embedded software developers from across the globe to present their design experiences on effective design flows, methods, and tool usage. The track offers a unique opportunity to network with and learn from other industry experts. The Designer Track co-chairs for 2017 include experts in design, verification and embedded systems:
· Zhuo Li, Cadence - Designer Track Chair
· Harry Foster, Mentor Graphics – Verification co-chair
· Steve Pagnos, XXX, Design co-chair
· Rob Oshana, NXP, Embedded/Automotive co-chair
Submissions may describe the application of tools to the design of a novel electronic system or the integration of EDA tools within a design flow or methodology to produce such systems. A submission may be problem-specific in scope (e.g., hardware/software-based architecture exploration, analyzing substrate coupling during floor planning) or may address a specific application domain (e.g., designing wireless handsets). The Designer Track differs from vendor-specific user forums in that it is not tied to a specific EDA vendor.
Regular submissions will be accepted in the following categories:
1. Front-end silicon design (FE): Front-end architecture, design and verification of current day system-on-chip (SoC) including major components such as CPU, GPU, and DSP. Front-end design of entire SoC sub-systems such as graphics, multimedia and modem.
2. Back-end silicon design (BE): Back-end design and verification of current day SoC, major sub-systems and constituent components (CPU, GPU and DSP). Relevant topics include (but are not limited to) physical design, clock tree generation, timing closure, verification, and design rule checking.
3. Embedded software and systems (ESS): Compilers (CPU, GPU, DSP) and programming aids, parallelizing tools, test and verification, operating system (including RTOS), virtual platform, virtual machines and run time environments.
The deadline for all Designer Track submissions is January 24, 2017. For additional submission information and deadlines, please visit www.dac.com under Call for Contributions.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems and for electronic design automation (EDA) and silicon solutions. Since 1964, a diverse worldwide community of many thousands of professionals has attended DAC. They include system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, and methodologies and technologies. A highlight of DAC is its exhibition and suite area featuring leading and emerging EDA, embedded systems, silicon, intellectual property (IP) automotive, security and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design Automation (ACM SIGDA).
Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.