Prospective authors are invited to submit a LBR paper (2 pages including references, two-column format) describing original work. Submissions that are accepted to the LBR program are required to have one author register to the conference and present a poster in the DAC LBR session. LBR does not encourage resubmission of papers rejected at other venues. If a paper is submitted to LBR, after an earlier version has been rejected, the authors should disclose major innovations or breakthroughs to earlier submissions. No duplicate or concurrent submissions are allowed.

Each submitted manuscript must discuss original work that has not been previously published in other indexed research databases. Authors are responsible for ensuring that their manuscript meets the submission guidelines outlined in this page. There will be no opportunity for resubmission to correct any issues. Your manuscript will be reviewed as a finalized manuscript. Preliminary submissions will be at a disadvantage.

• A submitter must enter the names, affiliations, cities, states, countries and email addresses of ALL the co-authors. The addition of new co-authors or reordering of authors will not be permitted after submission.

• Title may not be changed after the submission deadline.

• DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)' own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section. Make sure the PDF metadata does not contain the author information.

• The abstract of approximately 100 words must clearly state the significant contribution, impact, and results of the manuscript.

• The manuscript must be within 2 pages, double-columned, 9 or 10-pt font, in PDF format only, be a readable file and follow the ACM Template . The length and content of the submitted version and that of the final version (if accepted) should not be significantly different.

• A submitter is required to check the conflicts of interests (COI) field and the duplicate submission field. See the "Conflict of Interest" section and the "Duplicate Submission" section for

• Submitter must enter names, affiliations, city, state, country and email address of ALL co-authors. The addition of new co-authors will not be permitted after March 2, 2026.

• DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)’ own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section.

• The manuscript must be within 2 pages, double-columned, 9 or 10-pt font, in PDF format only, and be a readable file.

• Your draft manuscript must leave enough space to add authors, acknowledgements and other identifying information to the final version without exceeding 2 pages.

• Title should start with “Late Breaking Results: ...”

• The manuscript should focus on the contributions in these two pages and limit background and related work to the most essential.

• An author of each accepted LBR submission is required to register and present the corresponding poster at DAC 2026.

• Bring a poster following the instructions provided.

• Sign and submit a Rights and Release form.

An author of each accepted submission is required to:

• Produce a paper for the official conference proceedings.

• Sign and submit a copyright form.

• Register for DAC at the full conference registration rate (student rates are not eligible)

In addition:

• One co-author on the paper is required to pay the full conference Speaker Registration Fee; student rates may not be used. Each accepted paper requires a unique registration.

• The speaker must present the poster IN-PERSON at the conference. As part of the acceptance confirmation, international authors will be required to identify a North American presenter who will present the work if there are any issues with securing travel visas.

Following ACM’s policy on authorship, anyone listed as Author on a paper must meet all the following criteria:

• They have made substantial intellectual contributions to some components of the original work described in the paper; and

• They have participated in drafting and/or revision of the paper; and

• They are aware that the paper has been submitted for publication; and

• They agree to be held accountable for any issues relating to correctness or integrity of the work

DAC adheres to strict rules regarding duplicate submissions. Submissions must be clearly novel and distinct with respect to other submissions to 63rd DAC, concurrent submissions to other conferences and previously published work.

• All closely related work should be properly referenced. If such related work is authored by one of the co-author(s) of the manuscript in submission, it should be referenced as if it were written by others.

• Any extended version of the submitted manuscript should not be submitted or under review before the formal notification of DAC ‘s review decision.

• If any co-author has any paper that may be perceived as having overlapping contributions and that is simultaneously under review by another venue, such papers must be disclosed in the submission process.

Submissions which fail to follow the above guidelines will be automatically rejected. In serious cases, the authors’ names will be reported to IEEE & ACM and kept in records, as well as sent to the Technical Chair or the Editor of the venue where the duplicate manuscript was submitted; the authors may be banned from publishing at future DAC conferences.

When submitting to DAC, authors face a dilemma. DAC has a blind review process in which the author’s identity remains anonymous. However, the submission rules compel the authors to cite relevant publications that have already been accepted or are under review by another conference (such as ICCAD, DATE, ASP-DAC, etc.). Disclosing these papers under the citation list reveals the authors’ identities. To circumvent this issue, DAC has implemented a disclosure process.

When submitting a paper, the authors are asked to list each relevant paper that has not yet been published and include the corresponding pdf of the paper. The LBR Chair will be able to check for self-plagiarism and relevance without revealing the author identities to the reviewers. Failure to disclose such papers will be considered as omission of closely related work and subject to the same penalties outlined in the Duplicate Submissions, as discussed in the section.

In addition to the traditional areas of AI models, processor architectures, and platforms, DAC 2026 invites papers on AI frontiers in hardware design including Agentic AI for verification, synthesis, physical design and flow automation, foundation models for EDA, as well as benchmarks, data sets, and model evaluation for EDA. Papers on the impact of emerging GenAI in chip and system design are encouraged. The focus will be in disruptive ideas that address inefficiencies in traditional flows and significantly improve power, performance, and area while reducing the design effort.

AI1. AI/ML Frontiers for Hardware Design

• AI1.1 Benchmarks, data sets, and model evaluation for EDA

• AI1.2 Agentic AI for synthesis, physical design, and circuit design

• AI1.3 Agentic AI for verification

• AI1.4 AI-based chip design flow automation

• AI1.5 Foundation models for EDA

AI2. AI/ML Algorithms and Models

• AI2.1 Hardware-aware ML model development

• AI2.2 Efficient ML training, inference, and serving

• AI2.3 Approximation techniques for neural network training and inference

• AI2.4 Testing, debugging, and monitoring of ML applications

• AI2.5 Interpretability and explainability for ML models

AI3. AI/ML Application and Infrastructure

• AI3.1 Application-driven Al/ML learning/models/inferences

• AI3.2 Application-driven approximations in design for AI/ML

• AI3.3 Infrastructures for AI (including datasets, implementations)

• AI3.4 Interpretability and explainability for ML applications

AI4. AI/ML Architecture Design

• AI4.1 AI/ML accelerator, processing engine design and architecture

• AI4.2 Application-specific AI/ML architectures

• AI4.3 Approximation techniques for hardware architecture

AI5. AI/ML System and Platform Design

• AI5.1 Hardware/software codesign and co-optimization

• AI5.2 Specialized AI/ML system design

• AI5.3 Architecture-algorithm co-design for approximate computing

• AI5.4 AI/ML system modeling and simulation methodologies

• AI5.5 Evaluation and measurement of AI/ML systems

DAC is not only the leading conference in EDA, but also a vibrant hub for sharing cutting-edge progress in chip design technologies. From circuits to architectures, and from established methodologies to emerging frontiers like neuromorphic and quantum computing, DAC brings together diverse communities to exchange knowledge and spark innovation. The exchange helps the EDA community gain deeper insight into the evolving needs of design disciplines and fosters cross-domain collaboration to address shared challenges and opportunities.

DES1. SoC, Heterogeneous, and Reconfigurable Architectures

• DES1.1 Architectures for stochastic, statistical and approximate computing

• DES1.2 SoC and heterogeneous multi- and many-core architectures

• DES1.3 Run-time and design-time reconfigurable processor architectures

• DES1.4 2.5D/3D heterogeneous integration of compute, memory and communication platforms

• DES1.5 Fault-tolerant architectures

DES2A. In-memory and Near-memory Computing Circuits

• DES2A.1 Circuit techniques for near- or in-memory processing

• DES2A.2 Memory and storage technologies for in-memory and near-memory computing

• DES2A.3 Emerging technologies for in-memory and near-memory computing

• DES2A.4 Circuit-Inspired architectures for in/near-memory computing

DES2B. In-memory and Near-memory Computing Architectures, Applications and Systems

• DES2B.1 Near- or in-memory data management and processing models

• DES2B.2 Architectures for near- or in-memory processing

• DES2B.3 Memory and storage architectures for near- or in-memory processing

• DES2B.4 Data reorganization engines for specific applications

• DES2B.5 System/architecture interaction, execution model, interfaces

• DES2B.6 Specialized architectures for key workloads taking advantage of near- and -in-memory processing

DES3. Emerging Models of Computation

• DES3.1 Biologically-based or biologically-inspired computing systems

• DES3.2 Design automation for system & synthetic biology

• DES3.3 Neuromorphic and brain-inspired computing

• DES3.4 Neuromorphic and brain-inspired circuits

DES4. Digital and Analog Circuits

• DES4.1 Novel circuits for emerging AI/ML workloads

• DES4.2 Digital circuits and systems

• DES4.3 Analog circuits and data converters

• DES4.4 RF, wireless & wireline circuits and systems

• DES4.5 Imagers, MEMS, medical, and display circuits

• DES4.6 Circuits for memory design DES4.7 Power management circuits

• DES4.8 2.5-D and 3-D integrated circuit designs

• DES4.9 Circuit design for secure computing

DES5. Emerging Device and Interconnect Technologies

• DES5.1 New transistor structures

• DES5.2 Beyond-CMOS devices (e.g., steep-slope devices, spintronics)

• DES5.3 New process technologies (e.g. superconducting) DES5.4 Emerging interconnect and other nano-technologies

• DES5.5 Emerging non-volatile memory devices

DES6. Quantum Computing

• DES6.1 Quantum computing applications and algorithms

• DES6.2 Quantum computing hardware architecture and design

• DES6.3 Quantum computing technology

• DES6.4 EDA for quantum computing systems

As the premier conference in EDA, DAC invites cutting-edge research submissions in all aspects of design automation for circuits, chips, and systems. This includes both traditional optimization and the latest AI/ML-based technologies for automated chip and system design. The focus will be on breakthrough advancements that significantly improve power, performance, and area while reducing design effort and overall time to market.

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

• EDA1.1 System-on-Chip (SoC) specification, modeling, analysis, simulation, and verification

• EDA1.2 Application-specific processor design tools

• EDA1.3 Design tools for accelerator-rich architectures and heterogeneous multi-cores

• EDA1.4 Tools for reconfigurable computing

• EDA1.5 HW/SW co-design, interface synthesis, and co-verification

• EDA1.6 System-level methods for reliability and aging

• EDA1.7 3D/2.5D In-Package and On-Chip Communication architecture modeling and analysis

• EDA1.8 Synthesis and optimization of communication architectures

• EDA1.9 NoC architectures and design methodologies

• EDA1.10 Communication architectures using alternative technologies (e.g., nanophotonics, RF)

EDA2. Design Verification and Validation

• EDA2.1 Functional and transaction-level modeling and validation, coverage and test generation for hardware and embedded systems

• EDA2.2 Emulation and hardware acceleration

• EDA2.3 Formal and semi-formal verification and verification technologies

• EDA2.4 Verification of firmware, software, and hybrid hardware/software systems

• EDA2.5 Machine learning techniques for verification

• EDA2.6 Validation of cognitive systems

• EDA2.7 Verification on the cloud

EDA3. Timing Analysis and Optimization

• EDA3.1 Timing analysis and simulation/delay modeling

• EDA3.2 Signal integrity and noise analysis

• EDA3.3 Process technology modeling for timing analysis

• EDA3.4 Timing analysis and optimization for 3D/2.5D

EDA4. Power Analysis and Optimization

• EDA4.1 System-level low-power design analysis and management

• EDA4.2 Architectural power reduction techniques and analysis tools

• EDA4.3 Low-power circuit design methods and tools

• EDA4.4 Thermal analysis and management

• EDA4.5 Power analysis related process technology modeling

• EDA4.6 Power and thermal analysis and optimization for 3D/2.5D

EDA5. RTL/Logic Level and High-level Synthesis

• EDA5.1 Combinational, sequential and asynchronous logic synthesis

• EDA5.2 Technology mapping, cell-based design and optimization

• EDA5.3 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods

• EDA5.4 Synthesis for FPGAs

• EDA5.5 Synthesis for circuits in emerging device technologies

• EDA5.6 Synthesis on the cloud

EDA6. Analog CAD, Simulation, Verification and Test

• EDA6.1 Analog, mixed-signal, and RF design methodologies

• EDA6.2 Automated synthesis, place and route, and optimization of analog designs

• EDA6.3 Analog, mixed-signal, RF, electromagnetic, substrate noise modeling and simulation

• EDA6.4 Model order reduction techniques for analog/RF designs

EDA7. Physical Design and Verification

• EDA7.1 Floorplanning, partitioning, placement, and routing

• EDA7.2 Interconnect and clock network planning and synthesis

• EDA7.3 Cross-layer placement and routing optimization for timing/power/yield

• EDA7.4 Physical design of 3D/2.5D IC and package (e.g., TSV, interposer, monolithic)

• EDA7.5 Layout optimization for optical interconnects

• EDA7.6 Layout verification

• EDA7.7 Physical design on the cloud

• EDA7.8 Physical Design for secure computing

EDA8. Design for Manufacturability and Reliability

• EDA8.1 System/Design-technology co-optimization (STCO/DTCO)

• EDA8.2 Standard and custom cell design and optimization

• EDA8.3 Process technology characterization, extraction, and modeling

• EDA8.4 Reticle enhancement, lithography-related design optimizations and design rule checking

• EDA8.5 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact

• EDA8.6 Device-, gate, and circuit-level techniques for reliability analysis and optimization (e.g., soft error, aging, etc.)

• EDA8.7 3D/2.5D manufacturability, yield, and reliability

• EDA8.8 Post-Layout optimizations

EDA9. Test, Validation and Silicon Lifecycle Management

• EDA9.1 Fault modeling, ATPG, DFT, BIST, compression

• EDA9.2 Memory, FPGA, and emerging technology test and reliability

• EDA9.3 SoC, board- and system-level test

• EDA9.4 Post-silicon test, optimization, and defect diagnosis

• EDA9.5 Post-silicon validation and debug

• EDA9.6 Test for analog/mixed-signal/RF circuits

• EDA9.7 Silicon lifecycle management and system sustainability

• EDA9.8 Silicon health monitoring and predictive maintenance

The Security track at DAC covers the areas of privacy and security for AI/ML applications as well as AI/ML-based attacks and defenses, alongside hardware security fundamentals like cryptographic primitives, trusted system design, and post-quantum cryptography. Topics also address hardware-based threats and countermeasures, hardware supply chain integrity, and the intersection of AI/ML with hardware security. Additionally, the scope includes embedded architecture and cross-layer security techniques for cyber-physical systems, IoT, and cloud.

SEC1. AI/ML Security/Privacy

• SEC1.1 Privacy and security for AI/ML applications

• SEC1.2 AI/ML-based attacks and defenses

• SEC1.3 Adversarial machine learning attacks and defenses

• SEC1.4 AI/ML for cyber defense

• SEC1.5 Fairness for AI/ML applications

SEC2. Hardware Security: Primitives, Architecture, Design & Test

• SEC2.1 Hardware security primitives for cryptography, key generation, and authentication

• SEC2.2 Trusted IP and system-on-chip (SoC) design and manufacturing

• SEC2.3 Emerging technologies (Nanoscale devices, 3D, etc.) and security

• SEC2.4 Hardware security verification, validation and test

• SEC2.5 Post-quantum crypto algorithms and implementations

• SEC2.6 Design automation for security and privacy preserving

SEC3. Hardware Security: Attack and Defense

• SEC3.1 Hardware-enabled side-channel attacks and defenses

• SEC3.2 Hardware supply chain protection and anti-counterfeiting

• SEC3.3 Reverse engineering and hardware obfuscation

• SEC3.4 AI/ML-based hardware attacks and defenses

SEC4. Embedded and Cross-Layer Security

• SEC4.1 Embedded architecture, software and system-level techniques for security and privacy

• SEC4.2 Cyber-physical systems, IoT and edge security

• SEC4.3 Embedded security: metrics, models, verification and validation

• SEC4.4 Cloud security

• SEC4.5 Software-driven side-channel attacks and defenses

• SEC4.6 Privacy preserving computing

System design involves the design, selection, and integration of the right mix of hardware and software components to meet overarching goals such as speed, efficiency, reliability, security, and safety. Today’s systems span a wide range of applications—from mobile devices and medical equipment to automotive, robotics, drones, and industrial systems—making the field both diverse and dynamic. Embedded software plays a crucial role in devices that often aren’t recognized as computers, like thermostats, toys, defibrillators, and anti-lock braking systems, influencing both their operation and perceived quality. The SYS sessions at DAC showcase cutting-edge research in this area and serve as a platform for discussing the complex issues and future strategies for this rapidly evolving discipline.

SYS1. Autonomous Systems (Automotive, Robotics, Drones)

• SYS1.1 Autonomous Systems Design Tools and Methodologies

• SYS1.2 Autonomous Systems Architectures

• SYS1.3 Autonomous Systems Safety and Reliability

SYS2. Design of Cyber-Physical Systems and IoT

• SYS2.1 Cyber-physical systems and Internet-of-Things (IoT) platforms

• SYS2.2 Low-power and energy-efficient design techniques for IoT SYS2.3 Partitioned Edge/hub/cloud processing

• SYS2.4 Dependable and safety-critical embedded system design

• SYS2.5 Networking and storage system design

• SYS2.6 Advanced wireless communication system design

SYS3. Embedded Software

• SYS3.1 Embedded software verification methodologies

• SYS3.2 Embedded operating systems, middleware, runtime support, resource management, and virtual machines

• SYS3.3 Software techniques for multicores, GPUs, and multithreaded embedded architectures

• SYS3.4 Compilation strategies, code transformation and parallelization techniques for embedded systems

• SYS3.5 Domain-specific embedded libraries (e.g., for machine learning)

• SYS3.6 Embedded Software Development Case Studies (e.g., ANDROID development, ARM-based systems, RISC-V based systems etc.)

SYS4. Embedded System Design Tools and Methodologies

• SYS4.1 Embedded system specification, virtual prototyping and simulation

• SYS4.2 Embedded system synthesis and optimization

• SYS4.3 Analysis of embedded system QoS metrics - performance, battery life, reliability, etc.

• SYS4.4 Design methodologies for self-aware, self-adaptive and autonomous embedded systems

• SYS4.5 Design methodology for mobile, wearable and Internet of Things devices

SYS5. Embedded Memory and Storage Systems

• SYS5.1 On-chip memory architectures and management: Scratchpads, compiler controlled memories, etc.

• SYS5.2 Embedded storage systems organization and management

• SYS5.3 Memory and Storage hierarchies with emerging memory technologies

SYS6. Time-Critical and Fault-Tolerant System Design

• SYS6.1 Real-time analysis and tool flows

• SYS6.2 WCET methods and tools for embedded hardware/software systems

• SYS6.3 Mixed-Criticality system design

• SYS6.4 Fault-tolerant embedded system design

Submitters should report COIs of all co-authors with respect to members of the Technical Program Committee upon submission. However, it is recommended that submitters work on marking COIs as soon as they submit their manuscript's abstract, since this task may require some time, which is often scarce in the final sprint towards the completion of a manuscript's submission. Modifications to marked COIs can be made any time prior to the manuscript deadline.

Authors are asked to mark all the TPC members who have COIs with at least one of the authors at the time of abstract registration. Do not mark any members of the Technical Program Committee as COI where there is in fact no COI.

DAC assumes that authors have no additional COIs with TPC members, beside those that have been declared at the time of manuscript submission. If a manuscript is found to have failed in identifying a COI, during or after the paper selection process, the submitted manuscript will be automatically rejected. Same holds if members of the Technical Program Committee are marked as COI where there is in fact no COI.

The Call for Contributions lists several categories; please select the most appropriate primary topic when submitting your abstract. Authors of submissions that cover cross-cutting topics should select a category that is closest to the essential contribution of the submission. Submissions will be asked to select a broad category (e.g., “ EDA2. Design Verification and Validation”). A complete list of available categories and topic areas can be found in the CFP. Please note that there are separate categories for Artificial Intelligence, Design, Electronic Design Automation, Security, and Systems topics.

To satisfy the criteria for a blind review process, the Call for Contributions states that any references to the author(s) own previous work or affiliations in the bibliographic citations must be in the third person. For the blind review process, DO NOT LIST THE NAMES OR AFFILIATIONS OF ANY OF THE AUTHORS ANYWHERE ON THE MANUSCRIPT, except in the references section (if citation to prior work is required).

Example: A. and B. presented a method for listing self-referential citations in [5].


[5] A. A and B. B, How to write a research DAC paper, 2023.

DO NOT use “omitted for blind review” to cite authors’ own papers. Describe all related papers published by you as if they were written by others.

Citation of authors’ unpublished papers is not allowed, including citation of potential double and/or simultaneous submissions. If this situation arises, submitters must follow the disclosure requirements to disclose their (or their co-authors) related work that is under review or accepted for publication.

For additional information, please contact Jiang Hu, the 63 DAC Technical Program Committee Co-Chair.