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The DAC Back-End Design Track is one of the DAC Engineering Tracks and showcases cutting-edge solutions in digital and custom implementation for Systems on Chips (SoCs) and chiplets. It is the one-stop shop for the global community to interact, learn, and enrich themselves on all aspects of the digital implementation ecosystem.
Companies represented in the past include but are not limited to:
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The Back-End Design Track committee seeks high-quality and engaging submissions targeting challenges, innovations, and trends in digital and custom implementation. Topic areas span all aspects of back-end design – defined as getting from RTL to GDSII and preparation for manufacturing - including analysis, optimization, verification, manufacturing, and debug. Across these disciplines, the use of Machine Learning / AI in chip digital and custom implementation tools and flows is highly relevant, as is cloud adoption in design and verification tools and flows, including infrastructure and support.
Also of interest are submissions addressing unique application requirements and specific design flow challenges for advanced technologies, like safety, security, machine learning, cloud computing, and IoT, as well as industry specific requirements for automotive, consumer, mobile and wired communications and industrial applications.
The extended deadline to submit for Call for Contributions is January 20, 2026.
All accepted presentation and poster presenters are required to register for 63 DAC at either the Engineering or Full Conference registration rates; presentation is contingent on registering by April 24, 2026.
Submission Information
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The following are required for your submission:
The title of the presentation
Abstract of 100-200 words
Submission Categories
Presenter(s) name, affiliation, city, state, country, and email address
For evaluation by the Program Committee, a six (6) slides* PowerPoint presentation. Please review the guidelines below for suggested presentation structure.
*Additional information may be added in the notes section for each slide.
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The following guidelines should be followed when preparing your slides for submission:
Submissions are limited to 6 total slides*.
Submissions must be in PowerPoint format: 16:9 aspect ratio.
Consistent with DAC policy, company logos may appear only on the title slide.
Slide 1: Title, author names and affiliations
Authors may NOT be added after acceptance, so be sure to list all authors in the initial submission.
Slide 2: Motivation
Include an introduction that specifies the context and motivation of the submission. Examples: identify challenges associated with the design task at hand, clarify where in the design process the tools are used, and explain why the problem addressed is of interest to the audience.
Slide 3: Main Idea
Include details on the specific contributions of your work. Examples: innovative use of tools to achieve a specific goal, user enhancements to the tool and/or tool flow, dealing with scalability, details of integrating IP, study of design trade-offs, interfacing with manufacturing.
Slide 4: Additional Content Slide
Flexibility to add a slide that demonstrates value of the paper/idea
Slide 5: Evidence
Slide 6: Summary
Include a summary that highlights the main results of your work. Results are needed to evaluate the impact of your contribution. Metrics that could be used include productivity enhancement, improved quality of silicon, decreased complexity, and reduced time-to-market.
Important: Ensure that you have the necessary legal, trademark, copyright, and/or organizational approval needed to submit your presentation. Take appropriate steps to get this approval early, as the submission deadline cannot be extended.
*Note: The presentation format described above is what is required for your submission to be reviewed by the Technical Program committee to decide Accept/Reject. The final presentation delivered at DAC will be made up of a Title slide, Author slide and 12 content slides. The expectation is that the final presentation will expand on the submission presentation.
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Back-End Design Track submissions may describe the overall design and/or application of tools for creating the hardware, IP and/or software components of a novel electronic system. We specifically seek contributions from system engineers, hardware designers, teams leveraging cloud for design, application engineers, and vendor/customer teams.
Topic areas span all aspects of back-end design, analysis, optimization, verification, manufacturing, and debug of modern System-on-Chips (SoCs) and chiplets, including major components and sub-systems. Use of Machine Learning / AI in chip design and verification tools and flows. Cloud adoption in design and verification tools and flows, including infrastructure and support.
BE.01 Physical Synthesis and Design Techniques and Tools
BE.09 Analog, Mixed-Signal, and RF Design
BE.02 Clock Tree and Power Distribution Network Design and Optimization
BE.10 Custom, Standard Cell, FPGA Design Flows
BE.03 Timing and Circuit Analysis and Optimization
BE.11 3D Silicon Technology and Integration
BE.04 Reliability Analysis and Optimization
BE.12 Tool Integration, Design Analytics and Methodologies
BE.05 Interconnect Simulation and Analysis
BE.13 Design Planning/Power Planning/Floorplanning
BE.06 Timing/Power Sign Off Methodology
BE.14 Hardware Security: Modeling, Analysis and Synthesis, Device, Circuit and Architecture Techniques for Security, Hardware Security Verification and Validation, Hardware Support for Software and Security
BE.07 Design for Manufacturing
BE.15 Chip Architectures and Designs Targeting ML/AI Applications, System Design Targeting ML/AI Applications
BE.08 Manufacturing Test and Silicon Debug
BE.16 Cloud Adoption in Design and Verification Tools and Flows, Case Studies in Cloud Migration, Cloud Infrastructure for EDA Applications
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Accepted Engineering Tracks presentations and posters are NOT included in the DAC proceedings. However, accepted Engineering Tracks submissions (both posters and presentation slides) will be made available on the DAC website after the conference as a part of the DAC Archives (subject to approval from the authors).
Engineering Tracks submission will be accepted as a 15-minute presentation or presented as a poster in a 60-minute group session.
Best Presentation and Poster awards will be selected from the Engineering Tracks submissions. The awards will be based on (a) the quality of the submission, (b) the presentation given at DAC, and (c) the presentation at the poster session.
Timeline
Submission Selections
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Please select up to two of the following Topic Areas:
Artificial Intelligence (AI)
Security
Design
Systems
Electronic Design Automation
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Please select up to three of the following Keywords:
AI and Machine Learning
Formal/Static Methods
Analog & Mixed-signal Design
Low Power
Architecture & System Design
Logic & High-level Synthesis
Chiplets, Interconnects and 3D Integration
Manufacturing and Process
Circuits and Technology
Physical Design
Cloud Computing, Compute/Storage Infrastructure
Quantum Computing
Design Technology Co-optimization
Safety & Reliability
Embedded Systems and IoT
Security & Privacy
Emerging Technologies
Test and Design for Test (DFT)
FPGA Systems
Verification & Validation
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If a submission will be relevant to a specific industry or industries, one or more of the following industries may be selected:
Aerospace and Defense
Industrial
Automotive
Wireless Communications
Consumer
Wired Communications
Data Center
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