Research - Topics

In addition to the traditional areas of AI models, processor architectures, and platforms, DAC 2026 invites papers on AI frontiers in hardware design including Agentic AI for verification, synthesis, physical design and flow automation, foundation models for EDA, as well as benchmarks, data sets, and model evaluation for EDA. Papers on the impact of emerging GenAI in chip and system design are encouraged. The focus will be in disruptive ideas that address inefficiencies in traditional flows and significantly improve power, performance, and area while reducing the design effort.

AI1. AI/ML Frontiers for Hardware Design

• AI1.1 Benchmarks, data sets, and model evaluation for EDA

• AI1.2 Agentic AI for synthesis, physical design, and circuit design

• AI1.3 Agentic AI for verification

• AI1.4 AI-based chip design flow automation

• AI1.5 Foundation models for EDA

AI2. AI/ML Algorithms and Models

• AI2.1 Hardware-aware ML model development

• AI2.2 Efficient ML training, inference, and serving

• AI2.3 Approximation techniques for neural network training and inference

• AI2.4 Testing, debugging, and monitoring of ML applications

• AI2.5 Interpretability and explainability for ML models

AI3. AI/ML Application and Infrastructure

• AI3.1 Application-driven Al/ML learning/models/inferences

• AI3.2 Application-driven approximations in design for AI/ML

• AI3.3 Infrastructures for AI (including datasets, implementations)

• AI3.4 Interpretability and explainability for ML applications

AI4. AI/ML Architecture Design

• AI4.1 AI/ML accelerator, processing engine design and architecture

• AI4.2 Application-specific AI/ML architectures

• AI4.3 Approximation techniques for hardware architecture

AI5. AI/ML System and Platform Design

• AI5.1 Hardware/software codesign and co-optimization

• AI5.2 Specialized AI/ML system design

• AI5.3 Architecture-algorithm co-design for approximate computing

• AI5.4 AI/ML system modeling and simulation methodologies

• AI5.5 Evaluation and measurement of AI/ML systems

DAC is not only the leading conference in EDA, but also a vibrant hub for sharing cutting-edge progress in chip design technologies. From circuits to architectures, and from established methodologies to emerging frontiers like neuromorphic and quantum computing, DAC brings together diverse communities to exchange knowledge and spark innovation. The exchange helps the EDA community gain deeper insight into the evolving needs of design disciplines and fosters cross-domain collaboration to address shared challenges and opportunities.

DES1. SoC, Heterogeneous, and Reconfigurable Architectures

• DES1.1 Architectures for stochastic, statistical and approximate computing

• DES1.2 SoC and heterogeneous multi- and many-core architectures

• DES1.3 Run-time and design-time reconfigurable processor architectures

• DES1.4 2.5D/3D heterogeneous integration of compute, memory and communication platforms

• DES1.5 Fault-tolerant architectures

DES2A. In-memory and Near-memory Computing Circuits

• DES2A.1 Circuit techniques for near- or in-memory processing

• DES2A.2 Memory and storage technologies for in-memory and near-memory computing

• DES2A.3 Emerging technologies for in-memory and near-memory computing

• DES2A.4 Circuit-Inspired architectures for in/near-memory computing

DES2B. In-memory and Near-memory Computing Architectures, Applications and Systems

• DES2B.1 Near- or in-memory data management and processing models

• DES2B.2 Architectures for near- or in-memory processing

• DES2B.3 Memory and storage architectures for near- or in-memory processing

• DES2B.4 Data reorganization engines for specific applications

• DES2B.5 System/architecture interaction, execution model, interfaces

• DES2B.6 Specialized architectures for key workloads taking advantage of near- and -in-memory processing

DES3. Emerging Models of Computation

• DES3.1 Biologically-based or biologically-inspired computing systems

• DES3.2 Design automation for system & synthetic biology

• DES3.3 Neuromorphic and brain-inspired computing

• DES3.4 Neuromorphic and brain-inspired circuits

DES4. Digital and Analog Circuits

• DES4.1 Novel circuits for emerging AI/ML workloads

• DES4.2 Digital circuits and systems

• DES4.3 Analog circuits and data converters

• DES4.4 RF, wireless & wireline circuits and systems

• DES4.5 Imagers, MEMS, medical, and display circuits

• DES4.6 Circuits for memory design DES4.7 Power management circuits

• DES4.8 2.5-D and 3-D integrated circuit designs

• DES4.9 Circuit design for secure computing

DES5. Emerging Device and Interconnect Technologies

• DES5.1 New transistor structures

• DES5.2 Beyond-CMOS devices (e.g., steep-slope devices, spintronics)

• DES5.3 New process technologies (e.g. superconducting) DES5.4 Emerging interconnect and other nano-technologies

• DES5.5 Emerging non-volatile memory devices

DES6. Quantum Computing

• DES6.1 Quantum computing applications and algorithms

• DES6.2 Quantum computing hardware architecture and design

• DES6.3 Quantum computing technology

• DES6.4 EDA for quantum computing systems

As the premier conference in EDA, DAC invites cutting-edge research submissions in all aspects of design automation for circuits, chips, and systems. This includes both traditional optimization and the latest AI/ML-based technologies for automated chip and system design. The focus will be on breakthrough advancements that significantly improve power, performance, and area while reducing design effort and overall time to market.

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

• EDA1.1 System-on-Chip (SoC) specification, modeling, analysis, simulation, and verification

• EDA1.2 Application-specific processor design tools

• EDA1.3 Design tools for accelerator-rich architectures and heterogeneous multi-cores

• EDA1.4 Tools for reconfigurable computing

• EDA1.5 HW/SW co-design, interface synthesis, and co-verification

• EDA1.6 System-level methods for reliability and aging

• EDA1.7 3D/2.5D In-Package and On-Chip Communication architecture modeling and analysis

• EDA1.8 Synthesis and optimization of communication architectures

• EDA1.9 NoC architectures and design methodologies

• EDA1.10 Communication architectures using alternative technologies (e.g., nanophotonics, RF)

EDA2. Design Verification and Validation

• EDA2.1 Functional and transaction-level modeling and validation, coverage and test generation for hardware and embedded systems

• EDA2.2 Emulation and hardware acceleration

• EDA2.3 Formal and semi-formal verification and verification technologies

• EDA2.4 Verification of firmware, software, and hybrid hardware/software systems

• EDA2.5 Machine learning techniques for verification

• EDA2.6 Validation of cognitive systems

• EDA2.7 Verification on the cloud

EDA3. Timing Analysis and Optimization

• EDA3.1 Timing analysis and simulation/delay modeling

• EDA3.2 Signal integrity and noise analysis

• EDA3.3 Process technology modeling for timing analysis

• EDA3.4 Timing analysis and optimization for 3D/2.5D

EDA4. Power Analysis and Optimization

• EDA4.1 System-level low-power design analysis and management

• EDA4.2 Architectural power reduction techniques and analysis tools

• EDA4.3 Low-power circuit design methods and tools

• EDA4.4 Thermal analysis and management

• EDA4.5 Power analysis related process technology modeling

• EDA4.6 Power and thermal analysis and optimization for 3D/2.5D

EDA5. RTL/Logic Level and High-level Synthesis

• EDA5.1 Combinational, sequential and asynchronous logic synthesis

• EDA5.2 Technology mapping, cell-based design and optimization

• EDA5.3 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods

• EDA5.4 Synthesis for FPGAs

• EDA5.5 Synthesis for circuits in emerging device technologies

• EDA5.6 Synthesis on the cloud

EDA6. Analog CAD, Simulation, Verification and Test

• EDA6.1 Analog, mixed-signal, and RF design methodologies

• EDA6.2 Automated synthesis, place and route, and optimization of analog designs

• EDA6.3 Analog, mixed-signal, RF, electromagnetic, substrate noise modeling and simulation

• EDA6.4 Model order reduction techniques for analog/RF designs

EDA7. Physical Design and Verification

• EDA7.1 Floorplanning, partitioning, placement, and routing

• EDA7.2 Interconnect and clock network planning and synthesis

• EDA7.3 Cross-layer placement and routing optimization for timing/power/yield

• EDA7.4 Physical design of 3D/2.5D IC and package (e.g., TSV, interposer, monolithic)

• EDA7.5 Layout optimization for optical interconnects

• EDA7.6 Layout verification

• EDA7.7 Physical design on the cloud

• EDA7.8 Physical Design for secure computing

EDA8. Design for Manufacturability and Reliability

• EDA8.1 System/Design-technology co-optimization (STCO/DTCO)

• EDA8.2 Standard and custom cell design and optimization

• EDA8.3 Process technology characterization, extraction, and modeling

• EDA8.4 Reticle enhancement, lithography-related design optimizations and design rule checking

• EDA8.5 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact

• EDA8.6 Device-, gate, and circuit-level techniques for reliability analysis and optimization (e.g., soft error, aging, etc.)

• EDA8.7 3D/2.5D manufacturability, yield, and reliability

• EDA8.8 Post-Layout optimizations

EDA9. Test, Validation and Silicon Lifecycle Management

• EDA9.1 Fault modeling, ATPG, DFT, BIST, compression

• EDA9.2 Memory, FPGA, and emerging technology test and reliability

• EDA9.3 SoC, board- and system-level test

• EDA9.4 Post-silicon test, optimization, and defect diagnosis

• EDA9.5 Post-silicon validation and debug

• EDA9.6 Test for analog/mixed-signal/RF circuits

• EDA9.7 Silicon lifecycle management and system sustainability

• EDA9.8 Silicon health monitoring and predictive maintenance

The Security track at DAC covers the areas of privacy and security for AI/ML applications as well as AI/ML-based attacks and defenses, alongside hardware security fundamentals like cryptographic primitives, trusted system design, and post-quantum cryptography. Topics also address hardware-based threats and countermeasures, hardware supply chain integrity, and the intersection of AI/ML with hardware security. Additionally, the scope includes embedded architecture and cross-layer security techniques for cyber-physical systems, IoT, and cloud.

SEC1. AI/ML Security/Privacy

• SEC1.1 Privacy and security for AI/ML applications

• SEC1.2 AI/ML-based attacks and defenses

• SEC1.3 Adversarial machine learning attacks and defenses

• SEC1.4 AI/ML for cyber defense

• SEC1.5 Fairness for AI/ML applications

SEC2. Hardware Security: Primitives, Architecture, Design & Test

• SEC2.1 Hardware security primitives for cryptography, key generation, and authentication

• SEC2.2 Trusted IP and system-on-chip (SoC) design and manufacturing

• SEC2.3 Emerging technologies (Nanoscale devices, 3D, etc.) and security

• SEC2.4 Hardware security verification, validation and test

• SEC2.5 Post-quantum crypto algorithms and implementations

• SEC2.6 Design automation for security and privacy preserving

SEC3. Hardware Security: Attack and Defense

• SEC3.1 Hardware-enabled side-channel attacks and defenses

• SEC3.2 Hardware supply chain protection and anti-counterfeiting

• SEC3.3 Reverse engineering and hardware obfuscation

• SEC3.4 AI/ML-based hardware attacks and defenses

SEC4. Embedded and Cross-Layer Security

• SEC4.1 Embedded architecture, software and system-level techniques for security and privacy

• SEC4.2 Cyber-physical systems, IoT and edge security

• SEC4.3 Embedded security: metrics, models, verification and validation

• SEC4.4 Cloud security

• SEC4.5 Software-driven side-channel attacks and defenses

• SEC4.6 Privacy preserving computing

System design involves the design, selection, and integration of the right mix of hardware and software components to meet overarching goals such as speed, efficiency, reliability, security, and safety. Today’s systems span a wide range of applications—from mobile devices and medical equipment to automotive, robotics, drones, and industrial systems—making the field both diverse and dynamic. Embedded software plays a crucial role in devices that often aren’t recognized as computers, like thermostats, toys, defibrillators, and anti-lock braking systems, influencing both their operation and perceived quality. The SYS sessions at DAC showcase cutting-edge research in this area and serve as a platform for discussing the complex issues and future strategies for this rapidly evolving discipline.

SYS1. Autonomous Systems (Automotive, Robotics, Drones)

• SYS1.1 Autonomous Systems Design Tools and Methodologies

• SYS1.2 Autonomous Systems Architectures

• SYS1.3 Autonomous Systems Safety and Reliability

SYS2. Design of Cyber-Physical Systems and IoT

• SYS2.1 Cyber-physical systems and Internet-of-Things (IoT) platforms

• SYS2.2 Low-power and energy-efficient design techniques for IoT SYS2.3 Partitioned Edge/hub/cloud processing

• SYS2.4 Dependable and safety-critical embedded system design

• SYS2.5 Networking and storage system design

• SYS2.6 Advanced wireless communication system design

SYS3. Embedded Software

• SYS3.1 Embedded software verification methodologies

• SYS3.2 Embedded operating systems, middleware, runtime support, resource management, and virtual machines

• SYS3.3 Software techniques for multicores, GPUs, and multithreaded embedded architectures

• SYS3.4 Compilation strategies, code transformation and parallelization techniques for embedded systems

• SYS3.5 Domain-specific embedded libraries (e.g., for machine learning)

• SYS3.6 Embedded Software Development Case Studies (e.g., ANDROID development, ARM-based systems, RISC-V based systems etc.)

SYS4. Embedded System Design Tools and Methodologies

• SYS4.1 Embedded system specification, virtual prototyping and simulation

• SYS4.2 Embedded system synthesis and optimization

• SYS4.3 Analysis of embedded system QoS metrics - performance, battery life, reliability, etc.

• SYS4.4 Design methodologies for self-aware, self-adaptive and autonomous embedded systems

• SYS4.5 Design methodology for mobile, wearable and Internet of Things devices

SYS5. Embedded Memory and Storage Systems

• SYS5.1 On-chip memory architectures and management: Scratchpads, compiler controlled memories, etc.

• SYS5.2 Embedded storage systems organization and management

• SYS5.3 Memory and Storage hierarchies with emerging memory technologies

SYS6. Time-Critical and Fault-Tolerant System Design

• SYS6.1 Real-time analysis and tool flows

• SYS6.2 WCET methods and tools for embedded hardware/software systems

• SYS6.3 Mixed-Criticality system design

• SYS6.4 Fault-tolerant embedded system design

Please select up to two of the following Topic Areas:

Please select up to three of the following Keywords:

If a submission will be relevant to a specific industry or industries, one or more of the following industries may be selected: