The rapid growth of artificial intelligence (AI) applications is driving unprecedented demand for high‑performance, energy‑efficient AI accelerators, placing new and complex demands on Electronic Design Automation (EDA) flows. Scaling these designs from chips to full systems introduces challenges that traditional EDA methodologies were not built to handle.
With increasing accelerator size and complexity, traditional EDA tools and methodologies face challenges spanning advanced process nodes, large‑scale parallelism, and system‑level performance and data movement. These issues increasingly emerge at the boundaries between compute, memory, interconnect, and software behavior, where system‑level interactions has significant impact on design outcomes. In addition, the speaker will discuss the evolving landscape of EDA tools, highlighting the augmentation of conventional methodologies with AI-driven approaches to better address the increasing intricacy and verification demands in hardware design. Emerging trends such as hardware‑software co‑design, faster iteration through prototyping and comprehensive design‑space exploration are discussed as key approaches to addressing these challenges.
Attendees will leave with practical insights into current limitations of EDA at AI scale, emerging solutions being deployed in production environments, and the implications for next‑generation accelerator and system design – from silicon architects to EDA practitioners working across the full chips‑to‑systems stack.
