There is a rapid transition occurring in the world today - companies are driving from an internet economy to an AI economy. AI and HPC performance demands are increasing at a rapid clip and newer innovations in Si, Package and System designs are needed to meet the increased demand and to fully realize the power of AI. The demand for performance surged by nearly 10x over a two-year period (2021-2022), rapidly outpacing Moore’s Law, which traditionally doubles transistor counts roughly every 18 months. Performance and cost at the system level are key vectors that will require optimization across the entire stack to meet these demands. Heterogeneous integration of chiplets in an advanced package is essential to pave the way for sustainable scaling in the AI era.
In this presentation, I will cover our approach to chiplet design, advanced packaging, and interconnect technologies to ensure a fully optimized solution for AI needs. Intel as a system foundry is driving System Technology Co-Optimization (STCO) across the entire stack to achieve these goals. Intel has played a pioneering role in advancing chiplet-based architecture through its leadership in interconnect standardization, packaging innovation, and disaggregated design strategies and I will address key aspects in this talk.
