Design verification remains one of the most time-intensive and expertise-dependent stages of chip development, routinely consuming over 70% of total project effort. As AI agents mature from research prototypes into production tools, the DV community faces a pivotal question: are these systems actually ready for real tapeouts?
This talk presents lessons learned from deploying AI agents across production DV environments from block-level designs to full-chip SoC verification. We describe an agentic architecture that autonomously produces root-cause analyses and suggested fixes in under 15 minutes while operating under the realities of security, efficiency, and integration with existing flows..
Across a diverse set of production issues, we demonstrate a 70% end-to-end success rate on first-pass debug. We discuss what makes agents succeed and fail, and share how an AI-native EDA toolstack plus advanced layers for planning and institutional knowledge are foundational to achieving this level of reliability. This includes rethinking how agents access waveforms, query design databases, and interact with simulation infrastructure at scale.
We argue that the bottleneck to an AI-native EDA stack is no longer model capability — it is infrastructure, integration, and trust.
