Will Offer Look at Transitioning from Chip-Centric Design to System-Level Design
MUNICH, GERMANY –– October 12, 2016 –– Bob Smith, executive director of the Electronic System Design Alliance (ESD Alliance), will be the keynote speaker during the gala dinner hosted by the Design and Verification Conference (DVCon) & Exhibition Europe.
Smith’s dinner presentation, “Moore’s Law and the Transition from Chip-Centric Design to System-Level Design,” will be held Wednesday, October 19, at the Holiday Inn Munich City Center, in Munich, Germany, where DVCon Europe will take place October 19-20.
In his keynote speech, Smith will offer a perspective on how the semiconductor design ecosystem is evolving from a chip-centric focus to a system-centric worldview. According to the ESD...
Will be at HLDVT, DVClub San Jose, Design Solution Forum, DVCon Europe, FMCAD Exhibiting Formal Verification Tools, Presenting Tutorials, Chairing Sessions, Sitting on Panels
SAN JOSE, CALIF. –– September 28, 2016 –– OneSpin® Solutions, provider of innovative formal verification solutions for error-free digital integrated circuits (ICs), will sponsor and participate in a full complement of events, including workshops, meetings and conferences in California, Japan and Germany, in October.
The IEEE International High-Level Design Validation and Test (HLDVT) Workshop kicks-off the month Friday and Saturday, October 7 and 8. Dr. Raik Brinkmann, OneSpin’s president and chief executive officer, will participate in a panel titled, “Killer Apps: Not Your Father’s Formal Verification...
Dr. Strojwas Lauded for Pioneering and Sustained Contributions to Design for Manufacturing
San Jose, CALIF. –– September 27, 2016 –– Andrzej J. Strojwas, Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University, has been selected as the recipient of the 2016 Phil Kaufman Award for Distinguished Contributions to Electronic System Design (EDA).
The award is presented yearly by the Electronic System Design Alliance (ESD Alliance) and the IEEE Council on Electronic Design Automation (CEDA). The award ceremony and dinner will be held at the Fourth Street Summit Center in San Jose, Calif., Thursday, January 26, beginning at 6:30 p.m.
Dr. Strojwas is being recognized for his pioneering research in the area of design for manufacturing in the...
Formal Verification Experts from Both Companies Worked to Verify World’s Fastest and Fully Programmable Ethernet Switch Chip Design
MOUNTAIN VIEW, CALIF. –– September 22, 2016 –– Oski Technology, Inc., the world’s only dedicated formal verification service provider, today announced that its formal verification experts enabled Barefoot Networks, a pioneer in building user-programmable and high-performance forwarding planes, with verification of the design for the company’s Tofino™ switch chip. Barefoot’s Tofino chip processes packets at 6.5 terabits per second and is also fully programmable.
Barefoot Networks turned to Oski Technology for assistance with verifying the design of the Tofino chip, knowing that Oski had experience making formal verification scale to designs as...
NanoSpice Selected for Speed, and High Accuracy to Simulate Large Designs
SAN JOSE, CALIF. –– September 20, 2016 –– Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, integrated NanoSpice™, a high-performance parallel SPICE simulator from ProPlus Design Solutions, Inc., into its advanced SerDes transceiver intellectual property (IP) design and verification flow.
The parallel SPICE circuit simulator was selected for its speed, high accuracy and high capacity that enabled Credo Semiconductor to deliver its 56G PAM-4 SerDes IP on TSMC’s 16 nanometer (nm) FinFET Plus (16FF+) and FinFET Compact (16FFC) advanced process node. Previously, Credo’s engineering team had to partition its large designs into smaller blocks. With NanoSpice...
First IP Company in China to Become Alliance Member
San Jose, CALIF.–– September 7, 2016 –– C-Sky Microsystems, a leading supplier of 32-bit embedded CPU cores from Hangzhou, China, today became a voting member of the Electronic System Design (ESD) Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.
As the first intellectual property (IP) company from China to join the ESD Alliance, C-Sky intends to become an active member of the Semiconductor IP Working Group, helping develop a common methodology and best practices for IP fingerprinting. Other initiatives of interest to C-Sky include the Multi-Die Working Group and the Market Statistics Service (MSS) as well.
“The ESD Alliance’s broadened...
Silvaco’s Warren Savage to Head Semiconductor IP Working Group
San Jose, CALIF.–– August 30, 2016 –– The Electronic System Design (ESD) Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem, today announced Silvaco, Inc. as its newest member.
Silvaco, a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design, joined because it has a growing portfolio of production-proven intellectual property (IP) cores.
Additionally, Warren Savage, general manager of its IP Division, was named chair of the ESD Alliance’s Semiconductor IP (SIP) Working Group. The newly formed group will develop a common methodology and best practices for...
Wokingham, UK – 6th June 2016. EnSilica, a leading independent provider of semiconductor solutions and IP, and Micrium, the premier real-time operating system (RTOS) provider for embedded systems and the Internet of Things (IoT), have partnered to successfully port Micrium’s µC/OS-III® RTOS to EnSilica’s family of eSi-RISC processor cores. Micrium’s µC/OS-III is available on eSi-RISC with immediate effect. In addition, Micrium’s range of communication software, including its USB host/USB device and TCP/IP networking protocol stack, has been ported to EnSilica’s eSi-RISC.
“Recognized for its unparalleled reliability, performance and dependability, Micrium’s µC/OS-III RTOS is well-respected in the market and is a highly popular choice particularly for safety-critical and risk...
Comprehensive Guide Edited by Herb Reiter of eda 2 asic Offers Multi-Die Integration Techniques, Technologies, Vendor Listings
San Jose, CALIF. –– June 6, 2016 –– The Electronic System Design (ESD) Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem, today announced availability of the latest version of the Multi-Die integrated circuit (IC) Design Guide.
Version 2016.6 of the 300-page design guide has the latest background on multi-die integration techniques and technologies and includes information provided by vendors who offer multi-die IC design and manufacturing solutions and services. Edited by Herb Reiter of eda 2 asic, it is available as a free download from www.esd-alliance.org
Co-Sponsor of I LOVE DAC Named to Gary Smith EDA’s Must See@DAC List
SAN JOSE, CALIF. –– June 1, 2016 –– OneSpin® Solutions, deemed a “must see” exhibitor at the Design Automation Conference (DAC) by Gary Smith EDA, will showcase its entire line of innovative formal verification solutions for error-free digital integrated circuits (ICs) in DAC Booth #1249.
Additionally, OneSpin will use DAC to unveil its new corporate identity that includes refreshed branding, logo and website. The DAC Exhibit Floor will be open Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
“In the last four years, OneSpin has grown from a small company into the fifth largest logic verification supplier after the four major simulation...