Wokingham, UK – 6th June 2016. EnSilica, a leading independent provider of semiconductor solutions and IP, and Micrium, the premier real-time operating system (RTOS) provider for embedded systems and the Internet of Things (IoT), have partnered to successfully port Micrium’s µC/OS-III® RTOS to EnSilica’s family of eSi-RISC processor cores. Micrium’s µC/OS-III is available on eSi-RISC with immediate effect. In addition, Micrium’s range of communication software, including its USB host/USB device and TCP/IP networking protocol stack, has been ported to EnSilica’s eSi-RISC.
“Recognized for its unparalleled reliability, performance and dependability, Micrium’s µC/OS-III RTOS is well-respected in the market and is a highly popular choice particularly for safety-critical and risk...
Comprehensive Guide Edited by Herb Reiter of eda 2 asic Offers Multi-Die Integration Techniques, Technologies, Vendor Listings
San Jose, CALIF. –– June 6, 2016 –– The Electronic System Design (ESD) Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem, today announced availability of the latest version of the Multi-Die integrated circuit (IC) Design Guide.
Version 2016.6 of the 300-page design guide has the latest background on multi-die integration techniques and technologies and includes information provided by vendors who offer multi-die IC design and manufacturing solutions and services. Edited by Herb Reiter of eda 2 asic, it is available as a free download from www.esd-alliance.org
Co-Sponsor of I LOVE DAC Named to Gary Smith EDA’s Must See@DAC List
SAN JOSE, CALIF. –– June 1, 2016 –– OneSpin® Solutions, deemed a “must see” exhibitor at the Design Automation Conference (DAC) by Gary Smith EDA, will showcase its entire line of innovative formal verification solutions for error-free digital integrated circuits (ICs) in DAC Booth #1249.
Additionally, OneSpin will use DAC to unveil its new corporate identity that includes refreshed branding, logo and website. The DAC Exhibit Floor will be open Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
“In the last four years, OneSpin has grown from a small company into the fifth largest logic verification supplier after the four major simulation...
Abstracting underlying hardware & making IoT device software development more accessible to overcome IoT development limitations
Nantes, France, May 25, 2016 – IoT developers must cope with even more constraints than embedded developers (e.g., small footprints, low power considerations, faster prototyping to meet shorter time-to-market windows, connectivity to cloud platforms) and yet still produce top-quality, scalable, portable IoT software. The comprehensive IoT solution portfolio from MicroEJ® – MicroEJ Application Store, MicroEJ Studio, MicroEJ SDK, and MicroEJ OS – meets these challenges by enabling application-driven uses and business models on low-cost, resource-constrained embedded and IoT devices.
From 3:00-3:55pm on Wednesday, June 8th, Vincent Perrier, Chief...
On panel: “How Do We Make IP Reuse Work?”
Demonstrating SoC Design and IP Management Platform
FREMONT, Calif., May 24, 2016 – At DAC 2016, ClioSoft, the pioneer and leading developer of system-on-chip (SoC) design configuration and enterprise intellectual property (IP) management solutions for the semiconductor industry, will demonstrate the SOS Design Management Platform and IP Management solutions as well as participating on a panel in the IP Track. SOS is the EDA industry’s most widely installed design data and enterprise IP management solution for analog, RF, digital and mixed-signal designs. ClioSoft’s SOS platform is integrated with major EDA flows from Cadence Design Systems, Keysight Technologies, Mentor Graphics and Synopsys.
The 53rd DAC will be held this year...
Reinforces Verific’s Innovative Business Model to Jumpstart
Design Automation Entrepreneurial Efforts
ALAMEDA, CALIF. –– May 24, 2016 –– Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers, will showcase startup ventures Austemper Design, Innergy Systems and Tortuga Logic in its booth (#538) during the Design Automation Conference (DAC) June 5-9 in Austin, Texas.
Each will demonstrate versions of its design automation software Tuesday, June 7, and Wednesday, June 8, at:
10 a.m.-noon –– Austemper will showcase the way it adds robustness to intellectual property (IP) blocks by automatically inserting safety features required to meet medical, automotive and industrial industry regulations
noon-2 p.m. –– ...
Solido President Amit Gupta Joins Board
San Jose, CALIF. –– May 25, 2016 –– The Electronic System Design (ESD) Alliance (formerly the EDA Consortium), an international association of companies providing goods and services throughout the semiconductor design ecosystem, today announced its newly elected nine-member Board of Directors who will serve a two-year term.
Returning board members are:
• Aart de Geus, chairman and chief executive officer (CEO) of Synopsys, Inc.
• Dean Drako, president and CEO at IC Manage
• John Kibarian, president, CEO and co-founder of PDF Solutions, Inc.
• Grant Pierce, Sonics’ CEO...
Full Circuit Simulation Solutions Replaced Other Simulators for Small Block, Full-Chip Memory Designs
SAN JOSE, CALIF. –– May 23, 2016 –– UltraMemory Inc. (UltraMemory) has selected NanoSpice™ and NanoSpice Giga™ from ProPlus Design Solutions, Inc., the leading technology provider of giga-scale parallel SPICE simulation, SPICE modeling solutions and Design-for-Yield (DFY) applications, to simulate its super-broadband, super large-scale memory design.
UltraMemory is developing innovative 3D DRAM chip, which includes Through Chip Interface (TCI), enabling low-cost and low-power wireless communication between stacked DARM when compared to TSV technology.
Highly accurate and high-capacity SPICE simulation was necessary because it needed to simulate several DRAM chips with...
ISequenceSpec Automatically Generates Sequence for Verification, Firmware Validation
Used from Early Design through Post-Silicon Validation
LOWELL, MASS. –– May 24, 2016 –– Agnisys, provider of a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation, today announced availability of a portable sequence generator usable from early design and verification to post-silicon validation.
Patent-pending ISequenceSpec™ enables users to describe programming and test sequences of a device once and generate sequences automatically. It provides a straightforward specification format to describe the sequences and generates the code that ensures synchronization...
Cites New IP Working Group, Effective Long-Term Committees as Reason for Joining
San Jose, CALIF.–– May 19, 2016 –– Ridgetop Group of Tucson, Ariz., has become a voting member of the Electronic System Design (ESD) Alliance (formerly the EDA Consortium), an international association of companies providing goods and services throughout the semiconductor design ecosystem.
In joining the Alliance, Ridgetop Group, provider of advanced electronic prognostics and health management (PHM) solutions for electronic systems, semiconductor intellectual property (IP) blocks, and built-in self-test (BIST) solutions for critical applications, noted several initiatives that corresponded with its needs. They include the new Semiconductor IP Working Group to develop common methodology and best...