ALAMEDA, CALIF. –– May 23, 2017 –– Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, announced a licensing agreement with Austemper Design Systems, provider of an end-to-end functional safety solution.
SystemVerilog and VHDL parsers from Verific serve as the front end to Austemper’s software that analyzes, augments and verifies functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements.
Austemper will publically exhibit its Functional Safety Tool Suite for the first time at the Design Automation Conference (DAC) in Booth #1420 June 19-21 from10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
“Verific gave us a welcome boost to our development efforts,” remarks Sanjay Pillay, chief executive officer of Austemper. “The completeness of its Parser Platform and support infrastructure enabled us to fully concentrate our efforts on our expertise, functional safety. We were able to leave concerns about quality parsers to Verific and develop our tools serving the automotive, medical, industrial and enterprise markets quickly and cost effectively.”
“Austemper automates a critical and formerly manual aspect of the emerging functional safety space with its comprehensive tool suite,” says Michiel Ligthart, Verific’s president and chief operating officer. “Verific partnered with Austemper when it initially started and watched it grow into an impressive and formidable player in the functional safety market.”
Verific’s SystemVerilog, VHDL and UPF parsers are in production and development flows throughout semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compile on all 32 and 64 bit Unix, Linux, Mac and Windows operating systems.
DAC attendees can stop by the Verific Booth (#639) to learn more about its Parser Platforms and pick up this year’s giraffe giveaway. To schedule an appointment, contact Rick Carlson, Verific’s vice president of sales. He can be reached at (970) 948-9650 or via email at email@example.com. More information can be found on Verific’s website.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effectively. Since 1999, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: firstname.lastname@example.org Website: www.verific.com Or, follow Verific on Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/
Austemper Design Systems provides the industry’s only end-to-end tool suite to analyze, augment and verify functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements. Austemper of Austin, Texas, was founded in 2015 by experienced semiconductor professionals with the mission to provide a best-in-class solution to meet functional safety requirements of the automotive, industrial, medical and enterprise markets.
For more information, contact:
Public Relations for Verific