Agreement Offers Access to Semico Reports, Conference for ESD Alliance Members
San Jose, CALIF., and PHOENIX, ARIZ. –– April 19, 2016 –– The Electronic System Design (ESD) Alliance (formerly the EDA Consortium) and Semico Research today announced that they have entered into a cooperative marketing partnership to work together on several business initiatives in support of the semiconductor design ecosystem.
The partnership will enable the ESD Alliance and Semico, a semiconductor marketing and consulting research company noted for its coverage of the intellectual property (IP) market, to promote their common business goals. Semico will assist the ESD Alliance in broadening its reach into the IP community, a large part of the semiconductor design ecosystem, by promoting it at...
Chosen for Industry Experience, Vision to Support New ESD Alliance Mission
SAN JOSE, CALIF. –– April 13, 2016 –– Lucio Lanza, managing director of Lanza techVentures, has been appointed to the Board of Directors of the Electronic System Design (ESD) Alliance (formerly the EDA Consortium), an international association of companies providing goods and services throughout the semiconductor design ecosystem, it was announced today.
“I speak for everyone associated with the ESD Alliance in welcoming Lucio to our board,” says Bob Smith, the ESD Alliance’s executive director. “We are delighted he accepted our board’s invitation and look forward to his insights and understanding of the market to help propel the organization forward.”
Lucio Lanza, a well-known...
Move Reflects Expanded Scope, New Initiatives
SAN JOSE, CALIF. –– March 31, 2016 –– The EDA Consortium (EDAC) has moved into the future to become the Electronic System Design (ESD) Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.
During a launch event last night, Bob Smith, the ESD Alliance’s executive director, unveiled its new name and mission that broadens EDAC’s charter that was originally created to provide EDA companies with a forum to address cross-industry issues and promote the industry.
“The ESD Alliance reflects the sea change happening in the semiconductor industry as chip design takes a more system-oriented approach,” remarks Lip-Bu Tan, president and CEO of Cadence...
Yearly Award to be Presented to Robert Gardner during DATE’s Opening Ceremonies
ALAMEDA, CALIF. –– March 9, 2016 –– Robert Gardner, longtime member of the Verific Design Automation Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016.
He will receive the prestigious award in recognition of his long association and support of DATE during the Opening Ceremonies March 15.
Gardner was an active member of the DATE Executive Committee and Sponsor’s Committee, representing the EDA Consortium, where he served as executive director from 2006 until 2015. He was the co-chair of DATE’s Management Day Track, served on the DATE Audit committee, and continues to be...
Will Highlight New MEPro Platform for Circuit Design, CAD, Process Development
SAN JOSE, CALIF. –– March 8, 2016 –– ProPlus Design Solutions, Inc., the leading SPICE modeling, giga-scale SPICE simulation and design for yield (DFY) solution provider, will demonstrate its FinFET-ready DFY during TSMC 2016 Technology Symposia this month.
The TSMC North America events will be held March 15 in San Jose, Calif., March 22 in Boston, and March 24 in Austin, Texas.
Among the products to be demonstrated will be MEPro™, a new common platform for circuit design, CAD and process development teams. MEPro offers designers the means to quickly adopt and make full use of a process platform. They can evaluate any device or circuit target of one or multiple process platforms...
Unique Economic Factors Boost Simulation Performance, Throughput for SerDes Designs at 28nm, 16nm, 10nm
SAN JOSE, CALIF. –– March 8, 2016 –– Silicon Creations, supplier of high-performance semi-custom analog and mixed-signal intellectual property (IP), confirmed today it has deployed NanoSpice™, a high-performance parallel SPICE simulator from ProPlus Design Solutions, Inc., to simulate its SerDes interface IP designs.
The parallel SPICE circuit simulator is an important part of Silicon Creation’s design flow, used to boost simulation performance and throughput of both top-level and block-level simulations of SerDes IP designs in 28-, 16- and 10-nanometer (nm). “We’ve been impressed by the performance and accuracy of NanoSpice,” notes Randy Caplan, principal and co-...
Online Resource Designed to Serve Formal Verification Engineering Community
DVCon 2016 –– SAN JOSE, CALIF. –– March 1, 2016 –– FormalWorld.org, an online community dedicated to advancing the widespread use of formal verification, launched today during DVCon 2016 here with the goal to be the complete online resource for the expanding formal verification community.
Formal verification has become a critical technology in the modern verification flow. FormalWorld.org provides easy, open access to a range of helpful resources for an increasing number of end-users in need of education, information and peer-to-peer networking.
FormalWorld.org offers links to a broad range of information sources and will be updated on a continuous basis. Its monthly newsletter will...
Results Reported During Decoding Formal Club Meeting’s Checkmate Session, Award Ceremony Today
MOUNTAIN VIEW, CALIF. –– February 29, 2016 –– Results of the 2016 Oski Formal Puzzler “Chessboard Challenge” were announced today by Oski Technology, Inc., the only dedicated formal verification service provider, during the Decoding Formal Club meeting sponsored by Synopsys.
Oski challenged the Semiconductor Industry in December to solve two problems that involved moving a chess king around a 5-by-5 chessboard. Contestants were invited to use paper and pencil to solve the puzzles, but encouraged to run formal verification tools to solve them with model checking, a formal verification technique. Oski ran each entry using Synopsys VC Formal Solution to determine which Verilog...
Enables Early Bug Detection During Code Editing For FPGA, ASIC Designers
SAN JOSE, CALIF. –– February 9, 2016 –– OneSpin® Solutions, provider of innovative formal verification solutions, and Sigasi®, provider of hardware description language (HDL) design software, today announced the integration of the OneSpin formal-based design inspection software with Sigasi’s HDL authoring system Sigasi Studio XL.
The solution gives designers a way to run formal-based structural code checks within Sigasi’s environment at the point of edit, spotting issues that otherwise require additional verification effort. The use of formal techniques eliminates much of the false error-reporting characteristic common in rule-based linting tools, accelerating the verification process. Combining...
Close Collaboration Focused Around Specialized Formal IP Practice
SAN JOSE, CALIF. –– November 10, 2015 –– OneSpin Solutions™, provider of innovative formal solutions targeting a broad range of challenging verification problems, announced today that Boost Valley®, a pioneer of intelligent verification intellectual property (IP) and verification services, has joined the Spinnaker Certified Service Partners Program.
The Spinnaker Program, which offers a broad range of service expertise to meet a variety of verification needs, now includes a broader collaboration option known as Intelligent Verification IP (IVIP). Boost Valley as an inaugural member.
As a member of IVIP, Boost Valley has been trained and certified to offer services using either the 360 DV™...