Leading licensor of silicon IP for Video Coding – HEVC/H.265, AVC/H.264, and the full range of legacy formats – showcases stand-out performance of H.265 decoder using bitstreams from NGCodec
Belfast, UK and Sunnyvale, California – 23 May 2016 – AMPHION, the leading licensor of video codec IP cores for multimedia enabled System-on-Chip (SoC) integration, appears on the IP Pavilion [booth 1138] within DAC’s "World of IoT" exhibition zone to demonstrate in hardware the outstanding HEVC, AVC and legacy format decompression performance of Malone, the company’s silicon-proven, multi-format video decoder sub-system. Engineered by AMPHION’s highly experienced team of IP core designers, Malone has already been successfully deployed under various license arrangements in high-volume SoC...
9812D Selected for Technology Development at 28nm, 14nm and Beyond
SAN JOSE, CALIF. –– May 17, 2016 –– ProPlus Design Solutions Inc., today announced that United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a leading global semiconductor foundry, has adopted its 9812D wafer-level 1/f noise characterization system.
UMC selected 9812D from ProPlus, the leading technology provider of giga-scale parallel SPICE simulation, SPICE modeling solutions and Design-for-Yield (DFY) applications, to support its process development at the 28 nanometer (nm), 14 nm technology node and beyond. 9812D system has been widely adopted by leading foundries, integrated device manufacturers (IDMs) and fabless semiconductor companies worldwide for advanced process development and...
Powerful Specification Software Generates Accurate Implementation, Creates RTL Code, Firmware, Verification Models
Lowell, Mass. –– May 12, 2016 –– Agnisys, provider of a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation, today announced Istuary Innovation Group has licensed IDesignSpec™ (IDS) for its Enterprise Storage IC design and verification.
Registers contain hardware configuration settings and are the basis of the hardware/software interface. IDesignSpec is powerful register specification software for accurate implementation of addressable registers and the creation of register transfer level (RTL) code, firmware and verification models....
Longtime Customers Yogitech, Rocketick Acquired by Intel, Cadence, Respectively
ALAMEDA, CALIF. –– May 11, 2016 –– Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers, today announced that two of its longtime customers joined a growing list of other customers who have achieved successful exits through acquisitions.
Yogitech, a leading provider of services and solutions for functional safety, was acquired by Intel Corporation, while Rocketick Technologies Ltd., a leading provider of simulation acceleration solutions for chip verification, is now part of Cadence Design Systems. They follow other highly successful Verific licensees including, Denali, Forte and Jasper Design Automation who were acquired by Cadence. Synopsys purchased Atrenta and...
Plans Demonstrations on Full Formal Verification Solutions Portfolio,
Talk on HLS Coding Barrier, Presentation at DVClub Europe
SAN JOSE, CALIF. –– April 27, 2016 –– OneSpin® Solutions, provider of innovative formal verification solutions targeting a broad range of challenging verification problems, is set to participate at events in Europe and Israel in May.
It will be an exhibitor at CDNLive EMEA Monday, May 2, through Wednesday, May 4, at the Dolce Hotel Unterschleissheim in Munich, Germany. OneSpin will demonstrate its SystemC Formal Verification Solution developed in partnership with the Cadence Stratus High Level Synthesis (HLS) group. For information about CDNLive EMEA, visit: http://bit.ly/1W759Um
Dominik Strasser, OneSpin’s vice president of engineering, will...
SystemVerilog Parser Integrated with Prodigy Prototyping Platform
ALAMEDA, CALIF. –– April 19, 2016 –– Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry, announced today S2C, Inc., a leading provider of FPGA-based rapid prototyping solutions, licensed its SystemVerilog parser.
A longtime customer of Verific’s Verilog and VHDL parsers, S2C upgraded to Verific’s SystemVerilog parser and will integrate it into Prodigy, its rapid prototyping platform for exploring, navigating, analyzing, documenting and modifying large designs. S2C will license the software as source code, and will have access to Verific’s comprehensive support and maintenance.
“Verific continues to provide the best SystemVerilog...
Agreement Offers Access to Semico Reports, Conference for ESD Alliance Members
San Jose, CALIF., and PHOENIX, ARIZ. –– April 19, 2016 –– The Electronic System Design (ESD) Alliance (formerly the EDA Consortium) and Semico Research today announced that they have entered into a cooperative marketing partnership to work together on several business initiatives in support of the semiconductor design ecosystem.
The partnership will enable the ESD Alliance and Semico, a semiconductor marketing and consulting research company noted for its coverage of the intellectual property (IP) market, to promote their common business goals. Semico will assist the ESD Alliance in broadening its reach into the IP community, a large part of the semiconductor design ecosystem, by promoting it at...
Chosen for Industry Experience, Vision to Support New ESD Alliance Mission
SAN JOSE, CALIF. –– April 13, 2016 –– Lucio Lanza, managing director of Lanza techVentures, has been appointed to the Board of Directors of the Electronic System Design (ESD) Alliance (formerly the EDA Consortium), an international association of companies providing goods and services throughout the semiconductor design ecosystem, it was announced today.
“I speak for everyone associated with the ESD Alliance in welcoming Lucio to our board,” says Bob Smith, the ESD Alliance’s executive director. “We are delighted he accepted our board’s invitation and look forward to his insights and understanding of the market to help propel the organization forward.”
Lucio Lanza, a well-known...
Move Reflects Expanded Scope, New Initiatives
SAN JOSE, CALIF. –– March 31, 2016 –– The EDA Consortium (EDAC) has moved into the future to become the Electronic System Design (ESD) Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.
During a launch event last night, Bob Smith, the ESD Alliance’s executive director, unveiled its new name and mission that broadens EDAC’s charter that was originally created to provide EDA companies with a forum to address cross-industry issues and promote the industry.
“The ESD Alliance reflects the sea change happening in the semiconductor industry as chip design takes a more system-oriented approach,” remarks Lip-Bu Tan, president and CEO of Cadence...
Yearly Award to be Presented to Robert Gardner during DATE’s Opening Ceremonies
ALAMEDA, CALIF. –– March 9, 2016 –– Robert Gardner, longtime member of the Verific Design Automation Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016.
He will receive the prestigious award in recognition of his long association and support of DATE during the Opening Ceremonies March 15.
Gardner was an active member of the DATE Executive Committee and Sponsor’s Committee, representing the EDA Consortium, where he served as executive director from 2006 until 2015. He was the co-chair of DATE’s Management Day Track, served on the DATE Audit committee, and continues to be...