Demo Will Highlight How Design Teams Can Maximize Compute Capacity for Highly Scalable SPICE Simulations in the Cloud
SAN JOSE, CALIF. –– June 4, 2015 –– ProPlus Design Solutions, Inc., has partnered with Runtime Design Automation (RTDA) and Zentera Systems Inc. to demonstrate its SPICE simulation and design for field (DFY) software in the cloud at the 52nd Design Automation Conference (DAC).
NanoSpice™, a high-performance parallel SPICE simulator, and NanoYield™ statistical analysis from ProPlus will be managed by the NetworkComputer™ workload manager from RTDA, provider of infrastructure and design optimization software solutions. The tools will run on a public cloud powered and secured by the Zentera™ Cloud Overlay Network hybrid cloud solution.
Expands Safety Critical Formal Verification Solution for Automotive, Other Industry Segments Working With High-Reliability Design Constraints
SAN JOSE, CALIF. –– June 3, 2015 –– OneSpin Solutions™, provider of innovative formal solutions targeting a broad range of challenging verification problems, announced it will demonstrate its new OneSpin 360 Qualify™ product, formal fault qualification analysis for safety critical systems, during the 52nd Design Automation Conference (DAC) in Booth #3126.
OneSpin 360 Qualify accelerates and increases the precision of safety critical fault verification, an important part of the qualification process for ISO 26262 and other safety standards. The latest in a growing portfolio of formal verification apps, it formally identifies hard...
Decoding Formal Challenge, Lectures, Training Will Showcase
Completeness of End-to-End Formal Verification
MOUNTAIN VIEW, CALIF. –– June 3, 2015 –– (reminder June 8)
WHO: Oski Technology, Inc., the only dedicated formal verification service provider
WHAT: Will prove that its End-to-End formal testbench is complete and can catch all the design bugs at the 52nd Design Automation Conference (DAC)
WHEN: Monday and Tuesday, June 8-9, from 10 a.m. until 7 p.m. and Wednesday, June 10, from 10 a.m. until 6 p.m.
WHERE: Moscone Center, San Francisco
DAC attendees are encouraged to stop by the Oski Technology Booth (#1215) to challenge its End-to-End formal testbench. They can make a random or intentional change to an...
Grenoble – June 02, 2015.
Allegro DVT announces the immediate availability of its multi-format hardware video encoder IP with H.264/AVC, H.265/HEVC and VP9 support. This enhanced version of the Allegro DVT multi-format encoder IP now supports:
• H.264/AVC Baseline, Main and High Profile,
• H.265/HEVC Main and Main 10 Profile,
• VP9 Profile0 (8 bit) and Profile2 (10 bit),
for any resolution ranging from HD up to 4K@60Hz-10 bit.
This new IP brings 3 major benefits to our customers:
• Best-in-class video quality: Allegro DVT’s 10-year experience in advanced video codec design enables our customers to select the best trade-off between area, power and video quality according to their specific application needs.
Woodcliff Lake, New Jersey, and Suwanee Georgia — May 28, 2015 — Semiconductor intellectual property provider CAST Inc. and system IP and design firm SoC Solutions have partnered to give an advantage in productivity, functionality, and cost to developers in today’s competitive world of interconnected electronic devices.
Instead of starting from scratch, these developers of Internet of Things (IoT), Machine-to-Machine (M2M), and other connected applications can purchase ready-to-run hardware/software subsystems that perform the functions they need in an optimized fashion. The system experts at SoC Solutions develop these subsystems from CAST processor and peripheral IP cores and pre-integrated platforms, plus additional IP as needed. They integrate all the IP, add or develop...
First CAN FD IP core for ASICs and FPGAs now supports both CAN FD standards after rigorous transceiver chip testing at CAN Open Plug Fest
Woodcliff Lake, NJ — May 15, 2015 — A new version of the CAN 2.0 and FD Bus Controller Core that supports both the current non-ISO and upcoming ISO specifications is now available from intellectual property provider CAST, Inc.
The first CAN Flexible Data soft IP core for ASICs and FPGAs on the market (in January 2014), the controller core is also believed to be the first soft core to undergo testing at a CAN Open Plug Fest (in March 2015) and the first to support both Bosch’s original CAN-FD specification as well as the ISO version of the CAN FD specification expected to be ratified later this year. CAST sources the core from partner...
Will Highlight NVM IP's Ultra Low-Power, High-Performance, Availability on TSMC 180nm to 16nm Process Nodes, and How Antifuse Is the Future NVM Foundation IP Below 16nm
SAN JOSE, CALIF. –– May 28, 2015
WHO: Kilopass Technology, Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP)
WHAT: Will be a featured presenter at the 52nd Design Automation Conference (DAC) in the ChipEstimate Booth (#2433), the ICScape Booth (#1602) and the TSMC Booth (#1933)
WHEN: Monday, June 8 through Wednesday, June 10
WHERE: Moscone Center, San Francisco
Kilopass will present "Antifuse Memory: The New NVM Foundation IP" in the ChipEstimate booth (#2433) on:
Monday, June 8, at 1:30 p.m.
Tuesday, June 9, at 11:30 a.m.
Wednesday, June 10...
Will Feature New ARM Cortex-A72 Processor Model
ACTON, MASS. –– May 27, 2014
WHO: Carbon Design Systems® Inc., the leading supplier of accurate virtual prototype solutions
WHAT: Will demonstrate its system-level virtual prototype solutions and virtual prototype models during the 52nd Design Automation Conference (DAC) in the ARM® Connected Community Pavilion (Booth #2414). Also on display will be Carbon Performance Analysis Kits (CPAKs) for performance analysis, pre-silicon software development and accurate system benchmarking of advanced ARM processors and intellectual property (IP), including its new ARM Cortex®-A72 Processor model.
WHEN: Monday, June 8, and Tuesday, June 9, from 10 a.m. until 7 p.m. and Wednesday, June 10, from 10 a.m. until 6 p.m. ...
Designer, IP Track Poster Session to Feature "Secure System Design With Tortuga Logic's Prospect”
SAN DIEGO, CALIF. –– May 27, 2014
WHO: Tortuga Logic, transforming the way hardware designers and system architects test the security of hardware designs
WHAT: Will demonstrate its comprehensive Prospect Hardware Security Design and Analysis Toolkit at the 52nd Design Automation Conference (DAC) in the OneSpin Solutions booth (#3126)
WHEN: Monday, June 8, through Wednesday, June 10
WHERE: Moscone Center, San Francisco
Tortuga Logic’s Dr. Jason Oberg will participate in the Designer and IP Track Poster Session, discussing “Secure System Design with Tortuga Logic”s Prospect,” Tuesday, June 9, from 4:30 p.m. until 6 p.m. on the DAC Exhibit Floor.
More information about DAC can be...
WILSONVILLE, Ore., May 27, 2015
The Veloce® Power Application Software delivers:
• A complete solution that enables a new comprehensive methodology for power
-Accurate and early switching activity at the application level
-Early budgeting and tradeoff exploration at RTL
-Analysis and sign off at the gate level
• Real-time transfer of power switching activity, via a Dynamic Read Waveform API, to power analysis tools replacing current file-based activity transfer methodology
• Tight integration with an ecosystem of industry-recognized power analysis tools
For a technical whitepaper visit: http://www.mentor.com/products/fv/techpubs/download/?id=90538
Mentor Graphics Corporation (NASDAQ: MENT) today released the Veloce® Power Application...