The IP Track is targeted specifically at practitioners and is one of the DAC Engineering Tracks. Whether you are an EDA tool user, hardware designer, software engineer, IP provider, IP core user, application engineer, verification IP user, consultant, or an engineering manager, the IP Track is an ideal place to meet and share your experiences.
Companies represented in the past include but are not limited to:
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The IP Track is looking for submissions with timely topics and high-quality content targeting challenges, innovations and trends in IP architecture, design, integration, reuse, ecosystem, and verification of IP. This includes the unique application requirements and challenges for advanced technologies, automotive, security, Machine Learning, Cloud Computing and the Internet of Things. The scope also includes specific IP types such as security modules, off-chip interfaces, standard cells, mixed signal blocks and memories.
(As a note for those unfamiliar with the term IP, or with DAC’s use of this term: IPs are design building blocks that are integrated together to form a system comprising hardware and/or software components. System designers license the design and manufacturing specification of such IP from its owner, and include the IP with their own additional design elements to create a complete system.)
For each accepted submission, a presenter is required to register for DAC at either the Engineering or Full Conference registration rates; presentation is contingent on registering by April 10, 2027.
Submission Information
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The following are required for your submission:
The title of the presentation
Abstract of 100-200 words
Submission Categories
Presenter(s) name, affiliation, city, state, country, and email address
For evaluation by the Program Committee, a six (6) slides* PowerPoint presentation. Please review the guidelines below for suggested presentation structure.
*Additional information may be added in the notes section for each slide.
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The following guidelines should be followed when preparing your slides for submission:
Submissions are limited to 6 total slides*.
PowerPoint Template (Coming Soon!)
Submissions must be in PowerPoint format: 16:9 aspect ratio.
Consistent with DAC policy, company logos may appear only on the title slide.
Slide 1: Title, author names and affiliations
Authors may NOT be added after acceptance, so be sure to list all authors in the initial submission.
Slide 2: Motivation
Include an introduction that specifies the context and motivation of the submission. Examples: identify challenges associated with the design task at hand, clarify where in the design process the tools are used, and explain why the problem addressed is of interest to the audience.
Slide 3: Main Idea
Include details on the specific contributions of your work. Examples: innovative use of tools to achieve a specific goal, user enhancements to the tool and/or tool flow, dealing with scalability, details of integrating IP, study of design trade-offs, interfacing with manufacturing.
Slide 4: Additional Content Slide
Flexibility to add a slide that demonstrates value of the paper/idea
Slide 5: Evidence
Slide 6: Summary
Include a summary that highlights the main results of your work. Results are needed to evaluate the impact of your contribution. Metrics that could be used include productivity enhancement, improved quality of silicon, decreased complexity, and reduced time-to-market.
Important: Ensure that you have the necessary legal, trademark, copyright, and/or organizational approval needed to submit your presentation. Take appropriate steps to get this approval early, as the submissions deadline cannot be extended.
*Note: The presentation format described above is what is required for your submission to be reviewed by the Technical Program committee to decide Accept/Reject. The final presentation delivered at DAC will be made up of a Title slide, Author slide and 12 content slides. The expectation is that the final presentation will expand on the submission presentation.
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IP Track submissions may describe the overall design and/or application of tools for creating the hardware, IP and/or software components of a novel electronic system. We specifically seek contributions from system engineers, hardware designers, application engineers, and vendor/customer teams. Documented tool use may target electronic design and system design at all levels of abstraction and across all application domains. Regular submissions will be accepted in the following categories:
IP.01 IP Provider CPU / GPU / DSP / AI-ML-Accelerators
IP.07 IP sub-systems / Multi-discipline IP / Programmable logic IP
IP.02 IP Provider Memory Controller / NOC
IP.08 IP optimized for emerging markets and applications such as Automotive, IoT, Mobility, Networking, Cloud, Security, Resilience, Etc.
IP.03 IP Provider Communications IP
IP.09 IP Management / Assembly / Strategy / Roadmap
IP.04 IP Provider Analog / PHY / High speed interfaces
IP.10 IP Verification / Validation
IP.05 IP Provider Embedded Software
IP.11 Foundation IP / Standard Cells / Memories / PDKs
IP.06 IP Provider Configurable IP / IP Compilers
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Engineering Track submissions are typically accepted for one of the following categories:
Presentation: a 15-minute slot during an engineering session, combined with a poster
Poster gladiator: a 7-minute slot during a poster gladiator event on the exhibition floor, combined with a poster
Poster: a slot during the one hour poster session on one of the conference days
Accepted IP Track presentations and posters are not included in the DAC proceedings. However, accepted Engineering Tracks submissions (both posters and presentation slides) will be made available on the DAC website after the conference as a part of the DAC Archives (subject to approval from the authors).
Best Presentation awards will be based on (a) the quality of the submission, , (b) the pre-recorded presentation video, and (c) the presentation given at DAC.
Timeline
Submission Selections
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Please select up to two of the following Topic Areas:
Artificial Intelligence (AI)
Security
Design
Systems
Electronic Design Automation
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Please select up to three of the following Keywords:
AI and Machine Learning
Formal/Static Methods
Analog & Mixed-signal Design
Low Power
Architecture & System Design
Logic & High-level Synthesis
Chiplets, Interconnects and 3D Integration
Manufacturing and Process
Circuits and Technology
Physical Design
Cloud Computing, Compute/Storage Infrastructure
Quantum Computing
Design Technology Co-optimization
Safety & Reliability
Embedded Systems and IoT
Security & Privacy
Emerging Technologies
Test and Design for Test (DFT)
FPGA Systems
Verification & Validation
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Please select up to three of the following Keywords:
AI and Machine Learning
Formal/Static Methods
Analog & Mixed-signal Design
Low Power
Architecture & System Design
Logic & High-level Synthesis
Chiplets, Interconnects and 3D Integration
Manufacturing and Process
Circuits and Technology
Physical Design
Cloud Computing, Compute/Storage Infrastructure
Quantum Computing
Design Technology Co-optimization
Safety & Reliability
Embedded Systems and IoT
Security & Privacy
Emerging Technologies
Test and Design for Test (DFT)
FPGA Systems
Verification & Validation