EE Times Presents: The Future of Chiplets
Building Chips for the AI Era
Chiplets, or multi-die systems, present a solution to the insatiable demand for high-performance compute, faster time to market, and custom silicon designs from AI and other fast-growing use cases. They are key to scaling the performance of data centers up and out in a way that keeps power consumption under control, and are thus a key enabling technology on the path to artificial general intelligence.
The EE Times Chiplets in-person conference & Chiplet Pavilion exhibition at DAC 2025 will discuss the progress of chiplet technologies and the chiplet supply chain in all their complexity. The agenda will examine the entire value chain and ecosystem, spanning from initial concept and design exploration to packaging and testing. It will also explore the emergence of initiatives aiming to establish relevant technical standards and a chiplet marketplace.
We will also explore new product directions enabled by 2D and 3D designs, including large- and small-scale multi-die designs, and optical chip-to-chip connectivity.
Presentations will address chiplet standards and technologies, chiplet business models and real-world case studies of chiplet implementations.
Tuesday, June 24
Opening Remarks: The Chiplet Revolution will be Standardized: The New Building Blocks of Computing
Time: 10:40 AM
Eddie Ramirez, Arm, Vice President of Go-To-Market, Infrastructure Line of Business
AI is influencing mulitple workstreams, all of which have different requirements and outcomes. The diversity of these workloads is accelerating the move to custom silicon that is specialized for specific market needs. Chiplets offer a route to composable SoCs without the limitations seen in a typical silicon supply chain. This presentation will review chiplet strategies in play today, and how the market will realize new business models in the future.
Panel Discussion: Developing the Chiplet Economy
Time: 2:15 PM
Moderator: Nitin Dahad
The commercial chiplet ecosystem is rapidly evolving, driven by the need for greater scalability, performance, and cost efficiency. However, its growth is challenged by the lack of standardized interfaces, industry-wide collaboration, and the complexity of integrating chiplets from multiple vendors. Ensuring interoperability across different foundries, pre-validating components, and defining clear roles for system integration remain key challenges. Additionally, robust traceability and security mechanisms are critical for managing the multi-die supply chain. This session will explore the readiness of advanced packaging technologies, the role of design tool vendors, silicon makers, and IP providers, and the collaborative efforts required to establish a thriving chiplet economy
Wednesday, June 25
Opening Remarks
Time: 10:20 AM
Vladimir Stojanovic, Ayar Labs, CTO and Co-Founder
Panel Discussion: Enabling New Design Directions
Time: 11:10 AM
Moderator: Sally Ward-Foxton
Chiplets are redefining design possibilities, enabling breakthroughs in compute and memory integration, heterogeneous architectures, and solutions beyond the reticle limit. This session will explore the evolving industry landscape, the role of advanced design tools in ensuring high-performance chiplet-based systems, and the benefits and limitations of interconnect standards like UCIe and BoW. Key applications and market drivers will be examined. Finally, we will discuss the potential of optical chip-to-chip communication and its implications for the future of high-speed, efficient computing architectures in AI and beyond.
More information: https://chipletsatdac.eetimes.com/