| Poster Title: |
Gladiators |
| Powerdash: A Comprehensive Framework for SOC Power Analysis and Tracking |
Vivek Joshi, Atman Kar, Texas Instruments |
| High Coverage QA for Process Variability Compensation in LVS Rule Deck |
Heejae Lim, Jaeyoung So, Minho Jung, Jimin Yeo, Yunseong LEE, Bonhyuck Koo, Yongseok Lee, Ahmed Saleh, Mohamed Alimam, Samsung |
| A New Approach to Efficient Prelim Package Generation for Faster SOC Implementation |
Bhupendra Singh, Shoikat Das, Saurabh Srivastava, Anil Dwivedi, STMicroelectronics |
| Early Clock Tree Power Estimation and Correlation at SoC: A Case Study |
Sri Sai Pavan Pasumarthi, Sudheer Yadapalli, Vineet Ooramkumarath, Qualcomm |
| A Novel Flow to Verify SoC Integration with Formal Property Verification |
David Vincenzoni, Marcello Dusini, STMicroelectronics
|
| Virtual Instrumentation Based Predictive Checks for Shift-Left Low Power Verification |
Sachin Bansal, Yi Liu, Vijay Poosa, M.Vaishnavi Reddy, Nupur Gupta, Vishal Keswani, Amit Goldie, Manish Goel, Synopsys |
| Challenges and Improvements in StandardCell OpenAccess Content for Analog Design |
Anuradha Ray, Frederic Avellaneda, Stephan Weber, Anuradha Ray, STMicroelectronics |
| Methodology to Analyze and Optimize SOC Performance and Cost Using Function Agnostic Cycle Accurate Models |
Atul Lele, Anuvrat Srivastava, Ajeet Singh, Texas Instruments (India) Pvt. Ltd.; Ashutosh Mishra, Malaviya National Institute of Technology Jaipur |
| AI-Assisted Design Optimization for Extensive Design Spaces: Handling 260,000+ Combinations |
Austin Rhodes, Micron; Mohamed Atoua, Siemens |
| Struct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management IC |
Vijay Kumar, Keerthana K, Celeste Anil Lagali, Siemens |
| Smart Testing: Integrating Fault Simulation and AI/ML for Efficient IP Validation |
Himanshu Vishwakarma, Priyanka Gharat, Gopi Srinivas Deepala, Silicon Interfaces |
| A Decade of Evolution in Formal Verification |
Erik Seligman, Cadence Design Systems, Inc.; M V Kiran Kumar, Intel |
| Modeling Optimal Number of Tap-points for Flexible H-tree During Clock Tree Synthesis |
Anup Kumar, Akshay Mankotia, Cadence Design Systems, Inc. |
| Automated Floorplan Scaling Solutions and Framework |
Sivaramakrishnan Harihara Subramanian, Venkatesh RS, Khris Valencia Chacon, Intel |
| Executable Tables, 'A Journey from Document to Simulation Capable, Exemplified Using DDR5 ' |
Rahil Jha, Joseph Bauer, Rahil Jha, Cadence Design Systems, Inc. |
| Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips |
Piyush Jain, Rossana Liu, Hailang Wang, Apurva Soni, Medha Kulkarni, Pranav Ranganathan, Microsoft; Chidambaram Rakkappan, Amit Jangra, Godwin Rajasekhar, Sreekanth Rajan, Ansys |
| Die-Level Dynamic-IR Analysis Shift-Left Enabled by RedHawk-SC SigmaDVD |
Ruiqi Wu, Marc Zheng, UNISOC; Ran Zhang, Luca Cui, Chang Zhao, Ansys |
| COBRA : Code Coverage Measurement Technique for ARM-based firmware using Binary Modification Technology |
Wonchol Kim, Samsung |
| A Single Source Unified Approach to CSR Register Development |
Insaf Meliane, Andy Nightingale, Rich Weber, Arteris |