The 61st DAC Chips to Systems Conference Best Paper Awards
Event produced exceptional technical content and attracted thousands of attendees
SAN FRANCISCO, CA—
July 31, 2024 —The 61st DAC, The Chips to Systems Conference, and its sponsors – the Association for Computing Machinery (ACM), and the Institute of Electrical and Electronics Engineers (IEEE) – are pleased to announce the Best Paper and presentation award winners and authors. The Research Track Best Paper awards and Engineering Track Best Presentation awards are selected based on innovation, creativity, presentation quality and results. Each technical track has their own review committee that evaluates the final accepted paper, presentation and posters. For the 2024 event committee members reviewed final presentations, videos and submitted PDFs.
The 61st DAC – where the future of innovation for the design and design automation of electronic chips to systems can be found each year – had a 34% increase in research paper submissions (1,545) of which were 337 accepted papers across 29 tracks. In addition to the robust Research Track program is the Engineering Track program targeted for industry practitioners and technical managers, focusing on four key areas: front-end design, back-end design, IP and embedded systems and software. 2024 had a 32% increase in the number of Engineering Track submissions, with strong focus on AI, Design and IP.
The award winners were announced and recognized at the 61st DAC held June 23 – 27, 2024 at Moscone West, San Francisco, CA. The honorees and presentation abstracts can be found on the DAC website.
Best Paper Research Track Nominees:
- TITAN: A fast and Distributed Large Scale Trapped-Ion NISQ Computer
- LLM_HD: Layout Language Model for Hotspot detection with GDS Semantic Encoding
- ChatCPU: An Agile CPU Design and Verification Platform with LLM
- Token-Picker: Accelerating Attention in Text. Generation and Minimized Memory Transfer via Probability Estimation
Best Paper Research
Token-Picker: Accelerating Attention in Text. Generation and Minimized Memory Transfer via Probability Estimation
- Junyoung Park, Korea Advanced Institute of Science and Technology (KAIST)
- Myeonggu Kang, Korea Advanced Institute of Science and Technology (KAIST)
- Yunki Han, Korea Advanced Institute of Science and Technology (KAIST)
- YanG-Gon Kim, Korea Advanced Institute of Science and Technology (KAIST)
- Lee-Sup Kim, Korea Advanced Institute of Science and Technology (KAIST)
Best Presentation Designer Track - Front-End
Augmenting IP/SOC Verification Exhaustiveness with BER Transformer Infused Deep Learning Model
- Anil Deshpande, Samsung Semiconductor
- Somasunder Sreenath, Samsung Semiconductor
- Mukesh Barnwal, Samsung Semiconductor
- Rohan R. Swapnil Singh, Samsung Semiconductor
Best Presentation Designer Track – Back-End
UCI3-A 32GT/s Power Distributed Network Design-Optimization at Organic Interposer with Localized Integrated Passive Decoupling Capacitors
- Sheng-Fan Yang, Global Unichip Corporation
Best Presentation – IP Track
Considering Selective Resistance Extraction for Performance & Accuracy Trade-Off for Memory IP Simulation
- Praveen Kumar Verma, STMicroelectronics
- Anuj Dhillon, STMicroelectronics
- Harshit Sharma, STMicroelectronics
- Ashish Kumar, STMicroelectronics
- Vartul Sharma, Synopsys
- Rakesh Shenoy, Synopsys
Best Presentation – Embedded Systems Track
Complex Applications Mapping to Heterogeneous Compute Resources
- Wesley Skeffington, AMD
- Surya Chongala, AMD
- Deepak Shankar, Mirabilis Design
Engineering Track Poster Gladiator – Best Poster
Early Clock Tree Power Estimation and Correlation at SOC: A Case Study
- Sri Sai Pavan Pasumarthi, Qualcomm
- Sudheer Yadapalli, Qualcomm
- Vineet Ooramkumarath, Qualcomm
“In the three years since the pandemic, submissions to the DAC programs for both the research track and engineering track have consistently increased each,” said Vivek De, of Intel and the 61st DAC General Chair. “The selection process was difficult this year thanks to an increase in quality of papers and presentations to choose from. We commend the award winners for their hard work and encourage researchers and the design community to submit to the upcoming 62nd DAC.”
For 61 years, DAC has offered outstanding training, education, exhibits and networking opportunities for chip and system designers, researchers, software developers, IT engineers and software tool vendors.
For more information on the DAC, The Chips to Systems Conference or how to get involved at future DAC’s visit: www.dac.com.
About DAC
DAC, The Chips to Systems Conference (previously known as the Design Automation Conference) is recognized as the premier event for the design and design automation of electronic systems and circuits. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Over 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 150 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM's Special Interest Group on Design Automation (ACM SIGDA).
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For more information, please contact:
Michelle Clancy Fuller, 61st DAC Publicity Chair
Press@dac.com or call 1-503-702-4732